计数器 0 到 9999

基于DDS的BPSK调制器设计Verilog源码( U57FA u4E8.08 u868)

XAPP224 VHDL Data Recovery design file

6级流水，verilog实现浮点数的加法，其中浮点数格式符合IEEE754标准-6 water, verilog realize the floating point adder, in which floating-point format in line with the IEEE754 standard

说明：  利用stm32F407实现的等精度测频，可以精确测量频率，误差很小(The equal precision frequency measurement realized by stm32F407 can accurately measure frequency with little error.)

几个fpga竞赛的设计例-Several Example FPGA design contest

Altera大学计划程序包，基于Nios II的源代码-Altera University program package, based on the Nios II source code

说明：  实现在屏幕上显示绿色和红色相间的水平条纹。其中，vga_640x480模块将产生行同步信号hsyn和场同步信号 vsync; vga_stripes模块将产生red、green和blue三个输出。(The horizontal stripes of green and red are displayed on the screen. Among them, vga_640x480 module will produce line synchronization signal Hsyn and field synchronization signal vsync; vga_stripes module will produce red, green and blue three outputs.)

Code to controlling a Image sensor - CMOS(Code to controlling a Image sensor- CMOS)

AHB master总线verilog实现(Implementation of AHB master bus Verilog)

用PrimeTime的技巧，解决复杂时钟问题。(The world of telecommunications chips is full of messy clocking situations. This paper will cover the tricks and tehniques that author Paul Zimmer has developed to avoid the need to pour over reams of timing reports looking for problems. Best paper winner at SNUG San Jose 2001!)