NOC 模拟器

可以用于学习的示波器读取显示存储简单处理软件~希望可以对各位有用，用Verilog语言编写而成的,顶层加各个模块的分析，都有，希望有用~~~~~~~~~~~~~~~~~~~~~~

一个走马灯的程序,可以按照要求一个一个往后面按顺序点亮(A program for the lantern can be lit one by one according to the requirements.)

The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that can handle many forms of circuit design, including: * Custom IC layout * Schematic Capture (digital and analog) * Textual Languages such as VHDL and Verilog (The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that can handle many forms of circuit design, including:* Custom IC layout* Schematic Capture (digital and analog)* Textual Languages such as VHDL and Verilog)

EDA技术与VHDL课件，利用EDA技术进行电子系统设计(EDA technology and VHDL courseware, the use of EDA technology for electronic system design)

本文档对quartus与modelsim运用操作描述十分详细，对初学者，会有很大帮助！(Quartus and modelsim this document on the use of operations described in great detail, for beginners, there will be a great help!)

TI F28027 SCI 源码，中断，FIFO，LoopBack使能(TI F28027 SCI source code, interrupt, FIFO and Loopback enalbe)

说明：  AD9250是一款双通道14位ADC，最高采样速率250 MSPS，JESD204B Subclass 0或Subclass 1编码串行数字输出(The ad9250 is a dual channel 14 bit ADC with a maximum sampling rate of 250 MSPs and jesd204b sub class 0 or sub class 1 coded serial digital output)

由忆阻器机制设计蕴含逻辑，内含testbench仿真文件(Design implied logic by memristor mechanism, including testbench simulation file)

fpga 对sdram的读写 在quartus平台下可以仿真实现

数字时钟：数字钟是一种用数字电路技术实现时、分、秒计时的装置，与机械式时钟相比具有更高的准确性和直观性，且无机械装置，具有更长的使用寿命，已得到广泛的使用。 另外让我想到实验三的任务四就类似与做一个数字时钟，0分00秒到9分59秒，当时只是只实现了计数，暂停，清零的功能还有校分和报时的功能没有实现，于是就想自己做一个真正的时钟时分秒都能显示并且能清零、校分、整点报时。 做一个数字时钟，从00时00分00秒到23时59分59秒的数字时钟，其中一个开关管脚可以清零使数码管直接显示00时00分00秒，一个LED管脚整点报时，只要29分或者59分就亮一分钟，两个校分开关管脚一个用来拨快分显示器、一个用来拨慢分显示器，两个校时开关管脚一个用来拨快时显示器、一个用来拨慢时显示器。