NOC 模拟器

常用的锁相环技术，此程序是我在设计高频电路中运用的，具体见程序，经调试无问题(Commonly used phase-locked loop technology, this program is in the design I used in high-frequency circuits, see the specific procedures, no problem by debugging)

This CAN Controller was tested with the Bosch VHDL Reference Model and passed all the tests. Because of the licensing issue it can not be published on the Opencores web site. The Can Controller was also implemented in real HW (12 boards were constantly talking to each other). The included test bench is not a real test bench and should be improved. However a volunteer is needed for such a job. I can provide some help but am not willing to write it by myself.

约束所有时钟（包括你的设计中特有的时钟）对准确的时序分析结果而言是必不可少的。Quartus II TimeQuest Timing Analyzer为各种各样的时钟配置和典型时钟提供许多SDC命令。(Constraining all clocks, including the clocks unique to your design, is essential for accurate timing analysis results. The Quartus II TimeQuest Timing Analyzer provides many SDC commands for a variety of clock configurations and typical clocks.)

采用CORDIC算法的直接数字频率合成器的设计(CORDIC algorithm uses direct digital frequency synthesizer design)

说明：  通过一个计数器来实现输出信号的占空比要求，可以将duty_cycle分配到拨码开关上,LED分配到发光二极管上,然后调节拨码开关,即可看到LED的亮度发生变化.(The duty cycle of the output signal can be assigned to the dial switch by a counter, and the LED can be assigned to the light emitting diode. Then the brightness of the LED can be seen by adjusting the dial switch.)

应用背景此代码是移行为模型和添加乘数随着乘数和被乘数参数比特宽度关键技术Verilog 2001和Xilinx的Spartan 6 FPGA板试验台

四选一多路选择器,使用Verilog语言实现了多路选择器，可以通过FPGA实现四选一多路选择器，数字逻辑电路的相关内容。欢迎大家下载，使用vivoda打开，烧写在开发板上。

维特比译码，卷积编码，verilog编写，2,1,2编码(Victor than decoding, convolution code, verilog write, 2,1,2 coding )

用FPGA实现DDS波形发生器。可以实现方波，三角波，正弦波的切换，实现频率的调节。三角波和正弦波均用查表法实现。本文档包括一个主程序的代码，按键和显示的实例化程序代码、调用ROM生成的代码以及正弦波和三角波实现的数据表。

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