四选一多路选择器

The Date prototype object is itself a Date object (its [[Class]] is "Date") whose value is NaN.

此代码完成了流水线CPU的设计。其中有ALU，控制模块，UART等verilog代码。(This code completes the design of pipelined CPU)

6位密码锁，密码锁控制器是硬件与软件的结合。根据设计要求，决定以FPGA芯片和VHDL语言设计此电子密码锁(6 locks, the lock controller is a combination of hardware and software. According to design requirements, the decision to the FPGA chip and VHDL design electronic locks)

EDA技术与VHDL课件，利用EDA技术进行电子系统设计(EDA technology and VHDL courseware, the use of EDA technology for electronic system design)

FPGA控制m25p16flash芯片读写控制spi协议 可实现擦除写入读出功能(SPI protocol for read and write control of m25p16 flash chip controlled by FPGA Erase Write-Read Function)

此简化程序模拟并行进，串行出。在 Altera 开发板上成功实施。 在并行进，串行出的情况下，数据以串行方式接受，并且输出后一定数量的时钟周期。

基于FPGA的自适应滤波器的实现。采用Verilog编程，2阶滤波器。(FPGA-based realization of the adaptive filter. Using Verilog programming, 2-order filter.)

AD采集模块,设计模块采集AD5270的输出数据(AD Collection module Design module to collect the output data of AD5270 )

/功 能：1.实现与CPLD的通信,从而控制PWM的占空比. 2.实现LCD显示相关信息. // 3.实现对键盘按键的判断和确定相应的操作. 4.实现对电压电流的检测. // 5.实现过载保护功能,电流过大时,切断PWM输出,当排除过流故障后,自动恢复供电 // 6.实现用PID算法跟踪电压,实现稳压输出(/ Function: 1. Achieve communication with the CPLD to control the PWM duty cycle. 2 LCD Display relevant information.// 3. Realize the keyboard keys judgment and determine the appropriate action. 4. Achieve the voltage and current Detection// 5. achieve overload protection, current is too large, cut off the PWM output, when excluding overcurrent fault, automatically restore power// 6. achieve tracking voltage with PID algorithm to achieve the regulated output)

dds 频率可控，32位 输出为12位 已含有.hex文件，直接装载致ROM即可~(dds frequency-controlled, 32-bit output is 12 already contains. hex file can be loaded directly caused ROM ~)