Digital Cymometer VHDL procedures and simulation of the file name: plj.vhd.

本文通过大量的例子讲解VHDL。对于初学者来说是一本非常好的 教材-Based on the large number of examples of VHDL. For a newcomer it is a very good teaching

AHB master总线verilog实现(Implementation of AHB master bus Verilog)

生成一个M伪随机序列码，在ISE平台上可跑通(Generate an M Pseudo-Random Sequence Code which runs on ISE platform)

一款verilog设计的SRAM控制器，可以实现AHB总线控制的功能。(abcdefghijklmnopqrstuvwxyz)

我用VHDL写的正弦，用FPGA内部ROM，有仿真testbench,在quartus里可以运行。在板子里已经验证-I used to write VHDL sinusoidal, using FPGA internal ROM, has simulation testbench, you can run in Quartus. Yard has already been verified in the plates

vhdl adder with two input 4-bit and output of 4 bits and carry

32 bit RISC Processor with 3 stage pipeline

这是一个verilog代码实现的常用乘法器。设计的是通用N比特乘M比特的二进制乘法器(This is a common multiplier verilog code. Design of a generic N bits by M bits of the binary multiplier)

ARM7 VERILOG源码，非常精简，3级流水线(ARM7 VERILOG source code, very streamlined, 3-stage pipeline)

光纤通道协议，包括FC-SW,FC-FS,FC-LS,FC-GS,FC-HBA,FC-AE-ASM等文档。 (Fibre Channel protocols, including FC-SW, FC-FS, FC-LS, FC-GS, FC-HBA, FC-AE-ASM and other documents.)(Fiber channel protocol, including FC-SW, FC-FS, FC-LS, FC-GS, FC-HBA, FC-AE-ASM and other documents. (Fibre Channel protocols, including FC-SW, FC-FS, FC-LS, FC-GS, FC-HBA, FC-AE-ASM and FC-AE-ASM))