Digital Cymometer VHDL procedures and simulation of the file name: plj.vhd.

altera mvb fpga sopc 设计参考文档，有一定价值(mvb fpga sopc Design scheme)

AHB_Lite 通信协议的FPGA Verilog 设计(AHB_Lite communication protocol Verilog design in FPGA)

说明：  基于FPGA设计的串口发送及接收程序，波特率可调(FPGA - based serial port sending and receiving)

VHDL实例应用的经典，大家学习必看的书籍。-VHDL classic example of the application, see U.S. study books.

Simetrix搭建的一个光传输仿真工程，很好的学习参考。(Simetrix built an optical transmission simulation project, a good reference for learning.)

一款在Verilog实现的吃豆人游戏，采用VGA接口，在Nexys3开发板上运行无误。(A pac-man game implemented via Verilog, using VGA interface, perfectly run on Nexys 3)

0到255任意整数半整数分频Verilog HDL.rar-0-255 arbitrary integer half-integer frequency division Verilog HDL.rar

this a test keyboard code -this is a test keyboard code

文件名：ADC0809.vhd功能：基于VHDL语言，实现对ADC0809简单控制说明：ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟号，这里由FPGA的系统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。-File name: ADC0809.vhd features: Based on the VHDL language, easy to control implementation of the ADC0809 Description: ADC0809 internal clock does not need external 10KHz ~ 1290Hz clock number, here by the FPGA system clock (50MHz) frequency by 256 points to be clk1 (195KHz ) as the conversion ADC0809 clock job.

FIFO的verilog描述(Verilog description of the FIFO)