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baseband_verilog
verilog实现的基带信号编码,整个系统分为六个模块,分别为:时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器(verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum modules, polarity transform and interpolation modules, forming filter)
- 2009-10-08 10:19:34下载
- 积分:1
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adder
用于实现FPGA硬件开发使用的加法器,需要注意的是用Verilog语言实现的(The adder used to realize FPGA hardware development needs to be realized in Verilog language)
- 2020-06-22 03:20:01下载
- 积分:1
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VGA信号的产生
产生VGA彩条信号(Verilog 语言)-Generate VGA signal
- 2022-05-05 22:12:14下载
- 积分:1
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VHDL参考程序,他们的初学者参考使用
vhdl参考程序,供初学者参考使用-VHDL reference procedures, their use and reference for beginners
- 2022-04-19 08:23:59下载
- 积分:1
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RANGEN
2011年全国大学生电子设计竞赛E题“简易数字信号传输性能分析仪”fpga的控制代码,verilog编写;包括了M序列及同步时钟的提取等所有程序。(2011 National Undergraduate Electronic Design Contest E title "Simple digital signal transmission performance analyzer" fpga control code, verilog prepared including the M-sequence and synchronous clock extraction and all other programs.)
- 2020-10-27 17:09:59下载
- 积分:1
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8位大小比较器
说明: 8位大小比较器的VHDL源代码,Magnitude Comparator
VHDL description of a 4-bit magnitude comparator with expansion inputs(eight compared with the size of the VHDL source code, Magnitude Comparator VHDL description of a 4-bit magnitude comparator inputs with expansion)
- 2005-10-28 22:35:12下载
- 积分:1
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pylori
A VANET research program
- 2012-08-23 21:50:13下载
- 积分:1
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系统设计
说明: 基于数码管独立显示和三色灯的交通指示系统设计(Design of Traffic Indicator System Based on Digital Tube Independent Display and Tri-color Lamp)
- 2020-06-21 02:00:01下载
- 积分:1
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UART_CESHI
基于VHDL语言的串口发送和接收程序,自己调试通过,并已经运用在工程中(Based on the serial port to send and receive procedures VHDL language, its own debugging, and has been used in the project)
- 2016-08-05 15:27:54下载
- 积分:1
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CCPRRIzipP
一种基于CPRI标准的WCDMA NoddeB射频光纤拉远接口FPGA设计.pdf
(CPRI compliant the WCDMA NoddeB RF fiber pull far from the interface of the FPGA design. Pdf)
- 2012-07-19 22:29:39下载
- 积分:1