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verilogppt
北航夏宇闻的Verilog的PPT讲稿,挺经典的,适合初学者学习(Northern Xia Yu Wen' s Verilog the PPT script, very classic, suitable for beginners to learn)
- 2011-06-16 11:32:45下载
- 积分:1
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设计采用Verilog HDL 16位CPU。
design cpu 16 bits by verilog HDL.
- 2022-03-11 03:09:04下载
- 积分:1
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TOFED_Dataflow
Take its complement by applying DeMorgan’s theorem to obtain F in the form of product of complemented products.
- 2014-11-08 06:56:35下载
- 积分:1
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几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码
几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码-several VHDL source code, and in my preparation of a five pipelined RISC CPU code
- 2023-05-10 01:55:03下载
- 积分:1
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include UART port of VERILOG source, the program tested in FPGA, as chip design,...
包含UART口的VERILOG源程序,该程序在FPGA上验证通过,可作为芯片设计,或FPGA设计的一个完整IP核,硬件设计的兄弟们可参考一下。-include UART port of VERILOG source, the program tested in FPGA, as chip design, or FPGA design of a complete IP cores, hardware design brothers can make reference.
- 2022-06-01 13:44:15下载
- 积分:1
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An_enhanced_security_measures_DSP
通过总结当前对处理器架构的安全性能的处理方法,提出一种增强DSP处理器安全性能的方法。主要从并行性方面进行了改进。最后对改进的方法进行了仿真和结果分析。(By summing up the current security architecture of the processor performance approach, a DSP processor to enhance the safety performance of the method. Mainly from the aspects of parallelism to improve. Finally, improved methods and results of simulation analysis.)
- 2009-03-30 11:18:09下载
- 积分:1
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This program is Verlog language program, using QUARTUS6.0 preparation, program i...
本程序为Verlog语言程序,采用QUARTUS6.0编写,程序实现的功能是控制AD2S80的转换和和数据总线上数据的读取-This program is Verlog language program, using QUARTUS6.0 preparation, program implementation function is to control the conversion and AD2S80 and data bus to read data
- 2022-02-10 16:51:45下载
- 积分:1
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基于FPGA的钢琴演奏设计
本程序应用VHDL硬件描述语言,以QuartusⅡ8.0为开发工具设计了一个具有自动演奏乐曲功能的系统,演奏乐曲为《梁祝》,具有单曲播放器功能。本程序简单易懂,可作为FPGA入门学习之用。
- 2022-07-26 23:59:39下载
- 积分:1
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- 2022-12-14 10:50:03下载
- 积分:1
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Booth乘法器
- 2022-10-22 10:30:04下载
- 积分:1