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FPGA源代码
FPGA源代码公布,包括多进制数字频率调制VHDL程序FPGA驱动LCD显示中文字符“年”程序,LED静态显示ADC0809 VHDL控制程序,DAC0832 接口电路程序
- 2022-04-26 16:23:11下载
- 积分:1
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Short-Protograph-Based-LDPC-Codes-
LDPC码的短循环对LDPC码性能的影响
(Short Protograph-Based LDPC Codes)
- 2013-04-21 19:06:42下载
- 积分:1
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八线-三线优先编码器
基本的操作代码,a0-a7是八个信号输入端,a7的优先级最高,a0的优先级最低,当a7输入低电平0时,其他输入无效,编码输出y2y1y0=111;如果a7无效,而a6有效,则y2y1y0=110;
- 2023-05-02 18:40:03下载
- 积分:1
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SMBus
SMbus通讯协议的Verilog程序段,已通过Moldesim的仿真,可用(Verilog program segment of the SMbus communication protocol, has been through the Moldesim simulation, the available)
- 2021-03-24 18:29:15下载
- 积分:1
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Xilinx公司网站下的SDRAM Controller的参考设计,经过验证
Xilinx公司网站下的SDRAM Controller的参考设计,经过验证-Xilinx website of SDRAM Controller reference design, validated
- 2022-04-11 09:06:46下载
- 积分:1
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AD9957
ad9957的资料,内含有命令字生成器,适合使用该芯片的开发人员(ad9957 data, contains the command word generator for developers using the chip)
- 2011-10-27 22:06:55下载
- 积分:1
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Radix-8 Booth Encoded Modulo
vhdl 代码为基数 8 展位编码模块乘数与自适应延迟的高动态范围残留一些系统
- 2022-08-25 03:41:29下载
- 积分:1
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Detailed description of the FPGA design flow of the entire FPGA design flow full...
详细的说明了FPGA设计的整个流程
FPGA设计全流程Modelsim>>Synplify.Pro>>ISE-Detailed description of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE
- 2022-11-01 22:10:02下载
- 积分:1
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DTMB
能够完美产生数字地面电视(DTMB)的信源的程序。帧头模式为模式一。信道可选择,信号加入频偏,延时,后经滤波器后输出。(Able to produce perfect digital terrestrial television (DTMB) of the source program. Mode is the mode a header. Channels to choose from, the signal adding offset, delay, after the filter output.)
- 2013-07-25 11:22:28下载
- 积分:1
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dac7512
实现A/D转换,给定输入,观察输出电压,VHDL程序。(Implement A/D conversion,Given input, observe the output voltage, VHDL program.)
- 2016-04-21 16:05:49下载
- 积分:1