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61EDA_D888
基于Verilog HDL出租车计费系统的研制(Based on Verilog HDL Taxi Accounting System)
- 2010-01-07 18:30:10下载
- 积分:1
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4
通过监测工作状态实现带有IIC通讯功能的数据发送接收(to implement the sending and receiving data function of iic
communication )
- 2013-09-29 09:51:55下载
- 积分:1
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usbhostslave
说明: USB主机和设备的verilog代码,实现了USB1.1协议规范的要求(USB host and equipment Verilog code to achieve the USB 1.1 protocol specification requirements)
- 2005-09-13 11:34:09下载
- 积分:1
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VHDL子程序集,包括各种例程资料以及源码.
VHDL子程序集,包括各种例程资料以及源码.-VHDL subprogram, including a variety of routine information as well as the source.
- 2022-07-01 03:40:13下载
- 积分:1
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FIFO design
FIFo参考设计16x32 FIFO with simultaneous read/write operations.-FIFO design-16x32 FIFO with simultaneous read/write operations.
- 2022-03-30 00:49:06下载
- 积分:1
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Core1553BRT_EBR_EV_20
actel公司用于1553总线的1553BRT-EBR核心代码 包括文档和代码非常有用(Actel company for the 1553 bus 1553BRT-EBR core code, including documentation and code is very useful)
- 2021-05-06 18:58:37下载
- 积分:1
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基于FPGA的门级逻辑实现快速乘法运算的verilog源程序。
基于FPGA的门级逻辑实现快速乘法运算的verilog源程序。-FPGA-based gate-level logic implementation of rapid multiplication of the verilog source.
- 2022-02-21 06:32:58下载
- 积分:1
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Altera FPGA IP core of the source code for the use of Altera FPGA design to prov...
ALTERA的FPGA的IP核的源代码,为使用ALTERA的FPGA的相关设计提供参考.-Altera FPGA IP core of the source code for the use of Altera FPGA design to provide the relevant information.
- 2022-04-30 06:15:53下载
- 积分:1
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UART_real_time_clock
This is an UART real time clock
- 2009-06-07 01:21:41下载
- 积分:1
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用Actel公司的Fusion系列FPGA开发的LCD实验程序
用Actel公司的Fusion系列FPGA开发的LCD实验程序-Fusion with Actel s FPGA development series LCD Experimental procedures
- 2022-03-18 21:57:28下载
- 积分:1