PCIE_DM

本程序是fpga控制flash的读写程序，包括了程序和仿真时的测试文件(fpga flash)

10G高速以太网mac VERILOG源码 可仿真可实现(10G high speed Ethernet MAC verilog code can be used for synthesis or inplementation)

基于Verilog的FPGA时钟分频程序(FPGA clock frequency division program based on Verilog)

FPGA控制SJA1000实现CAN协议 适合深入学子FPGA的学生 很不错(FPGA control the SJA1000 CAN protocol for in-depth realization of the students are very good students FPGA)

basic cpu design in verilog

复旦cpu COS

硬件描述语言相关芯片程序源码Chip hardware description language-related program source code(Chip hardware description language-related program source Chip hardware description language-related program source code)

实验用16位全加器的VHDL代码，适合初学者学习，数电学习的好工具。 (Experiment with 16-bit full adder VHDL code for beginners to learn, a good tool to learn a few power.)

3x3中值滤波器的FPGA实现现(VERILOG)可直接使用。 (3x3 median filter FPGA implementation of the present (VERILOG) can be used directly.)

Actel的core8051，周立功在做，免费版没有片上调试功能、无跟踪寄存器、无硬件触发器，代码不可见