5分频电路

说明：  通过循环读写DDR3内存，了解其工作原理和DDR3控制器的写法，由于DDR3控制复杂，控制器的编写难度高，这里笔者介绍XILINX的MIG控制器情况下应用，是后续音频、视频等需要用到SDRAM实验的基础。(Through reading and writing DDR3 memory circularly, we can understand its working principle and the writing method of DDR3 controller. Because of the complexity of DDR3 control, it is difficult to write the controller. Here, the author introduces the application of Xilinx's MIG controller, which is the basis of SDRAM experiment for subsequent audio and video.)

n bit generic shift registers

用veriolg 语言编写的串口通讯程序，通过FPGA控制串口的通讯。(a veriog program completed on FPGA to contrlo a uart to communicaton with a computer )

用VERILOG实现自动售货机功能，运行正确，希望有帮助(Use VERILOG implementation vending machine function, correct operation, hope to have help)

基于FPGA的i2s接口输入模块设计，其中有原理图和verilog源码，可在Quartus环境下进行仿真(FPGA-based i2s interface input module design, including schematics and verilog source code, can be simulated in Quartus environment)

写一个单周期处理器运行一段mips指令，并包含mips指令转汇编码的程序(Write a single cycle processor to run a section of MIPS instruction)

说明：  采用vhdl语言编写的卷积编码（2.1.7），通过调试可直接下载使用(Convolution using vhdl language code (2.1.7) can be directly downloaded through the use of debugging)

verilog i2c master rtl+testbench 转自特权同学(verilog i2c master rtl+testbench)

Description of a sistolic arhictecture for a FFT implementation in FPGA.

This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.