FIR 滤波器石英项目

I2C slave功能模块的一种实现方式，简单易根据自己实际需求做修改，已经过FPGA验证可以很好的工作

介绍了在数字语音通信中, 利用在系统可编程技术和复杂可编程逻辑器件CPLD, 实现了数字语音的复接和分接 对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。实际应用结果表明, 系统工作稳 定可靠, 设计是成功的。(Describes the digital voice communications, the use of in-system programmable technical and complex programmable logic device CPLD, to achieve the digital voice multiplexer and demultiplexer for the single steady state in which the digital circuit and digital phase locked loop extraction bit synchronization signals are also carried out a detailed design specification. The practical application results show that the system works stable and reliable design is successful.)

自己写的_MIPS CPU，根据MIPS指令集设计，采用verilog编写，一步一步完善，结构简单清晰，可作为教学使用！        

说明：  Verilog AXI Components Readme GitHub repository: alexforencich verilog-axi

FPGA实验_HDB3编码器设计(包含5个模块)(FPGA design experiments _HDB3 encoder (including 5 modules))

原创，帧同步器的Verilog代码，在FPGA上验证实现过，无误。作为通信系统帧传输的仿真，有限状态机同步态和失步态的切换仿真。(Original Verilog code for frame synchronization, verify the implementation on the FPGA, and correct. Frame transmission as the communication system simulation, finite state machine synchronous state and the loss of the switching simulation of gait.)

VHDL实现国家SM4加密算法（ECB）模式 (VHDL to achieve national SM4 encryption algorithm (ECB) mode)

Simulation and Synthesis Techniques for Asynchronous FIFO Design

使用一个寄存器型参数来实现16位数据传完成后寄存器地址加1

说明：  用于读取海德汉绝对位置编码器的位置数据。ENDAT2.1接口(Read the data from ENDAT2.1)