FIR 滤波器石英项目

不同方法实现的CPU系统。同样支持加减乘，逻辑/算术移位，与或非等建议指令。(Different methods to achieve CPU system. Also supports, subtraction, multiplication, logic/arithmetic shift, and the like or recommend instruction.)

给予QPSK调制的OFDM例程，简单明了的表述了OFDM的通信原理(Given OFDM QPSK modulation routine, simple expressions of OFDM communication theory)

本代码是基于可编程门阵列flield视频图形阵列实现。该代码是使用Verilog

本例设计一个码率为500kb/s，字长为8 位、帧长为128 个字、帧同步码为EB90H 的PCM 采编器。用VHDL语言实现的。(This designs a code to lead for the 500 kbs|s, the word is long for 8, the growing is synchronous code of for 128 words and for the EB90 H of PCM adopt to weave a machine.Use what VHDL language carry out. )

图像处理的中值滤波器，使用verilog开发环境编程实现。(Verilog development environment programming median filter)

用verilog实现64点，128点，256点的fft(64 points, 128 points, and 256 points FFT are implemented with Verilog)

FPGA——IP_RAM实验： 创建IPRAM核，单端口，10位地址线（256字节），8位数据线（每字节8byte），读写使能 input [9:0] address; input clock; input [7:0] data; input wren; //置1则写入 output [7:0] q; LNXmode：控制LEDC显示 1：mode1，从k1~k3输入data的低4位，ledb计时，从0~f，计时跳变沿读取k1~k3的值，存入RAM 8个数之后，从RAM输出数据，用leda显示，同样每秒变化一次(The experiment of FPGA-IP_RAM: Create IPRAM core, single port, 10 bit address line (256 bytes), 8 bit data line (8 byte per byte), read and write enablement)

Description of a sistolic arhictecture for a FFT implementation in FPGA.

Verilog语言描述，统计图片的像素值直方图(Verilog，Pictures of the pixel value histogram statistics)

FPGA实现乒乓球游戏 代码及仿真 VGA实现(FPGA realizes table tennis game code and simulation VGA implementation)