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verilog2000更新部分,请对照前一个标准。加入了一些新的支持
verilog2000更新部分,请对照前一个标准。加入了一些新的支持-verilog2000 update, a former control standards. The inclusion of some new support
- 2022-02-04 06:03:56下载
- 积分:1
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c_fir_ppt
C语言写得FIR滤波器代码,简单实用,是学习滤波器设计的好材料,附带PPT滤波器设计说明(C language written FIR filter code, simple and practical, is a good learning materials of filter design, with PPT filter design
)
- 2020-07-04 03:00:02下载
- 积分:1
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newlin-pwm
VHDL 源码模块,可以实现最经典原PWM,可以用于电源,电机的控制()
- 2020-11-26 10:09:31下载
- 积分:1
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EDK_Tutorial_1
EDK tutorial 1 ----------------
- 2013-04-04 10:18:46下载
- 积分:1
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Simulation using VHDL language songs Andy Lau
用VHDL语言仿真歌曲刘德华的《月老》
-Simulation using VHDL language songs Andy Lau
- 2023-08-15 11:20:05下载
- 积分:1
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设计含异步清零和同步时钟使能的加法计数器
设计含异步清零和同步时钟使能的加法计数器-Clear design with asynchronous and synchronous clock so that the adder counter
- 2023-03-27 21:05:03下载
- 积分:1
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CPU-Project
说明: CPU设计,包含基本的指令集,能执行简单的程序。考虑了CPU,寄存器,存储器和指令集之间的关系。即读写寄存器,读写存储器和执行指令。(CPU design, including basic instruction set, to execute a simple program. Consider the CPU, registers, memory, and the relationship between instruction sets. That read and write registers, read and write memory and execution.)
- 2011-02-28 17:33:33下载
- 积分:1
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CSC_mat
彩色空间转换,RGB和YUV互转的matlab源码(RGB converting to YUV, YUV converting to RGB, Matlab source code)
- 2014-12-24 10:15:57下载
- 积分:1
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VHDL ip core的设计,软核的设计方法
VHDL ip core的设计,软核的设计方法-VHDL core of the design, soft-core design
- 2022-06-01 06:05:02下载
- 积分:1
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等精度数字频率计
的一个工程
等精度数字频率计
的一个工程---包括vhdl源程序和编译后产生的相关文件-Such as precision digital frequency of a project- including VHDL source code and compile the relevant documents after
- 2022-11-14 20:40:03下载
- 积分:1