设计含异步清零和同步时钟使能的加法计数器

用fpga实现SDI，每一步都很清楚 搞视频的可以参考(Fpga realization of SDI, each step are clearly engaged in the video can refer to)

说明：  FPGA与PC端实现串口数据的收发，先从PC端接收数据，然后发回给电脑，可通过串口助手验证。(The serial port data is sent and received between the FPGA and the PC. First, the data is received from the PC, and then sent back to the computer. It can be verified by the serial port assistant.)

高级verilog编程实现讲义，全英文讲义 -Senior verilog programming lecture notes, handouts in English

利用康芯公司的FPGA芯片设计制作频率计，实现对频率的测量。(Kang core using FPGA chip design company frequency meter, realize the frequency measurements.)

实现4倍抽取的CIC抽取滤波器模块的Verilog实现，在对数据进行抽取之前，首先进行滤波(Extracted 4 times realize CIC decimation filter module Verilog realize that in the data collected before the first filter)

vhdl的很多例子，包括LED、lcd、按键、数码管等等，非常的实用。-VHDL of many examples, including the LED, lcd, keypad, digital control and so on, very practical.

这是一个数字时钟的数字逻辑电路，整个工程打包上传，时钟可以计时、校时、整点报时、定时闹钟。使用电路图实现的。在quatarsII里面仿真的并且下载到DE2板上运行过。-This is a digital clock digital logic circuits, the whole project package upload, the clock could be time, school hours, the whole point timekeeping, timing alarm clock. The use of circuit implementation. The quatarsII inside the simulation, and downloaded to the DE2 board to run-off.

随机数发生器

用PrimeTime的技巧，解决复杂时钟问题。(The world of telecommunications chips is full of messy clocking situations. This paper will cover the tricks and tehniques that author Paul Zimmer has developed to avoid the need to pour over reams of timing reports looking for problems. Best paper winner at SNUG San Jose 2001!)

4x4鍵盤使用語法為VHDL，基於cyclone(4 x 4 keyboard using VHDL)