设计含异步清零和同步时钟使能的加法计数器

VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.(SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the )

this is code verilog

synopsys的systemc和RTl书籍清晰电子版，专业权威的EDA公司的培训资料(synopsys of systemc and RTl clear electronic version of books, professional authority of the EDA company' s training materials)

xilinx公司提供的关于FPGA硬件设计的额时序约束参考资料-xilinx provided on the FPGA hardware design timing constraints of the amount of reference material

此代码完成了流水线CPU的设计。其中有ALU，控制模块，UART等verilog代码。(This code completes the design of pipelined CPU)

一个AD4003的测试/控制程序，2Ms/s，18bit的AD高速AD芯片(A AD4003 test / control program, 2Ms/s, 18bit AD high speed AD chip)

异步FIFO控制器的Verilog设计与实现-Asynchronous FIFO controller Verilog Design and Implementation

是使用VHDL语言编写的基于FPGA的uart的源代码！-VHDL language is to use FPGA-based uart source code!

UG二次开发，课程作业，研究生，学习，初学者，打孔，复杂体，阵列 UG C program，homework，student，study，first，hole，complex，many( UG C program，homework，student，study，first，hole，complex，many)

按键控制led灯亮灭顺序，从左到右跑或者从右往左跑(Press button to control the LED lights on and off)