设计含异步清零和同步时钟使能的加法计数器

嵌入式系统的乘法器试验报告 包括源代码 用VHDl语言编写-Embedded System multiplier test report including source code language used VHDl

verilog HDL编写的出租车计费系统-verilog HDL prepared Taxi Accounting System

说明：  PID算法用verilog语言实现，实测可用，由三个模块组成(The PID algorithm is implemented in Verilog language. The actual measurement is available. It consists of three modules.)

用verilog语言写的简单的键盘扫描代码，适合初学者，用alter的软件编写的程序代码。(Using verilog language to write simple keyboard scan code, suitable for beginners, with alter software program written code.)

有符号16位乘法器。经典booth编码。拓扑结构为wallance树。加法器类型是进位选择加法器。(Number system: 2 s complement Multiplicand length: 16 Multiplier length: 16 Partial product generation: PPG with Radix-4 modified Booth recoding Partial product accumulation: Wallace tree Final stage addition: Carry select adder )

实现pwm波的输出，按键可调占空比的，可通过连接pwm输出值led灯以检测占空比的变化(To realize the output of the PWM wave, key adjustable duty ratio, but through the connection PWM output value led lamp with testing duty ratio changes )

FFT处理器设计及其应用研究，适合做fpga信号处理的技术人员参考-FFT processor design and applied research, suitable for signal processing fpga technology reference

成为真正的网页制作的高手的话,必须了解并使用DHTML.这里提供了最好的手册和文档.-become truly a master pages, then have to understand and use DHTML. Here to provide the best manuals and documents.

说明：  实现电子密码锁的各项功能,经过编译和仿真(Electronic code lock of the function, the compiler and simulation)

在Quartus环境中，采用VHDL语言编写的出租车计费系统，系统共分为分频、状态切换、记程、计费等模块，模仿现实中出租车计费。-In the Quartus environment, the use of VHDL language taxi billing system, the system is divided into sub-frequency, state switching, recording process, billing and other modules, to imitate reality, taxi billing.