设计含异步清零和同步时钟使能的加法计数器

实现一个简单的电子钟，其时间（时，分，秒）可以设置和更改，设置和更改的同时不会影响其他显示的变化（相互独立）。-achieve a simple electronic bell, the time (hours, minutes and seconds) can set and change, Settings and change will not affect the other shows the change (independent).

Disparity mapp code in VHDL

Vhdl实用教程，可帮助初学者迅速掌握VHDL的编写-Vhdl practical tutorials to help beginners to grasp quickly the preparation of VHDL

the 8 bit alu by verilog

vhdl学习基本编写程序，关于温度的读取和显示，vhdl学习基本编写程序，关于温度的读取和显示，vhdl学习基本编写程序，关于温度的读取和显示

XAPP224 VHDL Data Recovery design file

用Verilog实现1602的配置及功能。正确编译与实现(Realized by Verilog 1602 configurations and functions. Compilation and implementation of the right)

Verilog很不错的进阶书!看完后对数字模拟集成电路设计有个深入的认识!-This book is very important for a designer who wants to design a great digital circuits!

Verilog reference book

AMBA总线apb总线的verilog代码以及相关的中断控制。(AMBA bus apb bus verilog code and associated interrupt control.)