用VHDL语言实现的LDPC码的硬件语言实现，对比验证…

有关FPGA芯片的管脚的封装的一些资料。-Pin on the FPGA chip packaging some of the information.

MAX481、MAX483、MAX485、MAX487-MAX491以及 MAX1487是用于RS-485与RS-422通信的低功耗收发器， 每个器件中都具有一个驱动器和一个接收器(The MAX481, MAX483, MAX485 The MAX487-MAX491, and MAX1487 low-power transceivers for RS-485 and RS-422 communication, each device has a drive and a receiver)

利用电话远程系统，通过密码验证来实现对家庭电器的智能控制。-The use of long-distance telephone system, via a password to verify the implementation of the intelligent control of household electrical appliances.

VHDL描述的时钟分频电路，用途广-VHDL description of the clock divider circuit, uses widely ...

基于FPGA器件的DDS设计实现中的一个核心部分就是波形存储表的设计。首先采用LPM_ROM和 VHDL选择语句这两种方法进行波形存储表的设计和比较分析 然后考虑到硬件资源的有限性及DDS的精度要 求,对这两种方法的程序进行了优化 最后对这两种方法设计的程序进行仿真和硬件调试。结果表明:采用这两种 方法都能有效地实现DDS中波形存储表的设计。 (DDS-based FPGA devices designed to achieve one of the core of the waveform is stored in table design. First of all, choose to adopt LPM_ROM and VHDL statements of these two methods for the design waveform storage tables and comparative analysis and then, taking into account the limited hardware resources and the accuracy of DDS, the two methods to optimize the process the last of these two methods of process design simulation and hardware debugging. The results showed that: the use of these two methods are all effective ways to achieve the DDS waveform stored in the table design.)

design through verilog hdl

采用Quartus2编写的电子秒表电路 实现计时、暂停等功能(Quartus2 prepared using electronic stopwatch timer circuit, suspension and other functions)

基于FPGA/EP2c5的开发板详细例程，内容丰富，简单易懂(Development board based on more routine FPGA/EP2c5, content rich, easy to understand)

这是rs（255，223）编码的verilog源程序。里面有：encode、decode、test－bench等文件。(This is rs (255,223) verilog source coding. Inside : encode, decode, test-bench and other documents.)

周立功Fusion StartKit，fpga开发板的实验例程，Flash Memory初始化RAM实验(ZLG Fusion StartKit, fpga development board test routines Flash Memory Initialize RAM experiments)