design through verilog hdl

自己用verilog编写的crc16-ccitt码的产生，是并行的。(Crc16-ccitt code written in verilog generate parallel.)

找到这本书的完整版了。呵呵，贴出来和大家共享。这是本好书，我买了一本作为Verilog的参考书。这本书语法部分集中，便于查阅，此外讲了很多实用的设计思想。最重要的是本书薄，可以完整看完。强烈推荐。 （如果只是查阅，电子版就可以，如要完整学习，建议还是买纸质版的）(Find the full version of this book. I posted and share. This is a good book, I bought a reference book as Verilog. Syntax in this book section focuses on ease of reference, in addition to speaking a lot of useful design ideas. The most important thing is that the book is thin, you can complete reading. Highly recommended. (If you only access the electronic version to complete learning, suggestions or to buy the paper version))

spi driver: Analog Device DAC ad9788 SPI Controller

VHDL_count 从 0 到 9 4 7 段 LED 显示 4 脉冲使 （đếm 慈 0 đến 9 hiển 施耐 4 带领 7 đoạn với 4 xung 启用）

NiosII的C代码,包括网卡,lcd,usb,串口,按键.(NiosII C code, including network cards, lcd, usb, serial, key.)

一款8位Turbo-51的CPU软核的设计-An 8 Turbo-51" s soft-core CPU design ....

verilog code for 3 bit sequence detector

数字时钟6位数码管显示。主要器件为74ls48和74ls160 /74ls161。功能：1.显示时、分、秒。2. 可以24小时制或12小时制。3. 具有校时功能(Digital clock six digital tube display. Main components of 74ls48 and 74ls160/74ls161. Features: 1. Shows hours, minutes, seconds. (2) a 24-hour or 12-hour clock. 3 a school function)

实现音频的I2S通信，音频柱的显示，及其噪声的处理等功能(Realization of audio I2S communications, audio column display, and its noise processing, and other functions)

SPI总线硬件描述语言Verilog下的实现，含主模式和从模式的实现，经过仿真验证，可作为一个单独的模块使用(SPI bus under the Verilog hardware description language to achieve with the main mode and slave mode realization, through simulation, can be used as a separate module uses)