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4x4-key
4*4键盘小程序 两种算法内附检查LED(4* 4 keyboard applet containing two algorithms check the LED)
- 2013-07-28 22:19:49下载
- 积分:1
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verilogCRC32
32位bit输入的CRC32校验,verilog的代码,以及modelsim的testbench代码(The encode of CRC32 with 32bit-inputs based on verilog, and according encode of testbench)
- 2012-03-07 10:22:58下载
- 积分:1
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请注意: 本例的源描述包含文件类型,在学习版上不能编译及模拟, 如果您需要对此描述进行编译及模拟,请与北京理工大学 ASIC研究所联系。 另外,此例与第...
请注意: 本例的源描述包含文件类型,在学习版上不能编译及模拟, 如果您需要对此描述进行编译及模拟,请与北京理工大学 ASIC研究所联系。 另外,此例与第75例是同一个电路的不同部分的描述,可以 一起参考这两个例子的描述。-Please note : The cases include the description of the source file type, version of the study can not be compiled and simulation, if you need to compile this description and simulation, Beijing Polytechnic University and the Institute of ASIC link. Additionally, the cases of 75 cases with the first of a circuit with the different parts of the description, reference together two examples of this description.
- 2022-06-30 03:50:17下载
- 积分:1
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Electronic code locks, FPGA
电子密码锁,采用基于fpga的设计,可以设置6位密码-Electronic code locks, FPGA-based design, can be set 6 password
- 2022-04-06 21:28:08下载
- 积分:1
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spi_slave
xilinx 平台的SPI从接口实现源码,供参考学习(used xilinx,slave-spi interface.)
- 2019-04-21 12:08:29下载
- 积分:1
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apb timer
说明: 是基于apb总线下的timer外设的rtl代码,主要包括apb_timer的master逻辑verilog,以及相应的开发文档,包括寄存器的描述,功能特性等。(RTL code is based on timer peripheral under APB bus, which mainly includes master logic Verilog of apb_timer and corresponding development documents, including the description of registers, functional characteristics and so on.)
- 2019-01-25 16:54:02下载
- 积分:1
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FPGA讲义适合中等以上读者,主要是FPGA的一些高级应用
FPGA讲义适合中等以上读者,主要是FPGA的一些高级应用-FPGA notes for readers more than moderate, mainly a number of advanced applications FPGA
- 2022-06-16 08:29:17下载
- 积分:1
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alpha-beta
阿尔法贝塔滤波器,是卡曼滤波器的简化,比卡曼滤波器速度快。这是一个实例。(aplha-beta filter is filter that faster than kalman filter)
- 2020-11-25 20:09:31下载
- 积分:1
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gamefive
高精度小数除法器设计与实现。
在FPGA开发板上实现小数除法器,输入输出信号N_in [15:0], D_in[15:0],N_in[15:0]小于D_in,即被除数小于除数,输出商Q_out[15:0]中Q[15]一定为0,Q[14:0]为商的小数部分。输入和计算结果通过VGA显示。(Precision fractional divider design and implementation. In the FPGA development board fractional divider, input and output signals N_in [15: 0], D_in [15: 0], N_in [15: 0] less than D_in, ie the dividend is less than the divisor, quotient output Q_out [15: 0] in Q [15] necessarily 0, Q [14: 0] for the business of the fractional part. Input and calculation results display by VGA.)
- 2017-01-01 17:32:25下载
- 积分:1
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ulpiereport.tar
开源的ULPI IP核,可用于USB3300芯片的开发(openSource ULPI IP core which could be used for USB3300 chip development)
- 2020-07-02 06:40:02下载
- 积分:1