一种基于FPGA的通用微处理器设计

用CPLD驱动数码管，实现从0000计到9999，数码管是用动态显示，程序用VERILOG完成的-CPLD drives with digital control, of from 0000 to 9999, digital control is a dynamic display, the program completed with VERILOG

四人抢答器，已通过编译，仿真，包括抢答识别、计分、计时、数字显示等功能。-Four Responder, has passed the compilation, simulation, including the answer in his identification, scoring, timing and digital display.

关于5-11APSK在高斯信道中的误码率分析仿真程序，对具体调制方式及解码方式都有详细的过程(About 5-11APSK in Gaussian channel bit error rate analysis simulation program, has a detailed specific modulation and decoding process)

VHDL实现SPI接口转I2c接口的源代码，可以直接调用-VHDL realize I2C interface SPI interface to the source code, you can directly call

verilog语言编写的jtag（边界扫描模块），初学的时候可以看看(verilog language jtag (boundary scan module), a novice when you can look)

ad9230的配置程序，差分输入输出，verilog(ad9230 configuration program, verilog)

QPSK调制的载波频偏估计，是一个可以调用的函数。接收端进行了一系列的处理。经典的Fitz法(QPSK-carrier frequence offset estimation_ Fitz)

产生VGA彩条信号(Verilog 语言）-Generate VGA signal

载波同步，costas环，基于Verilog的载波同步环(Carrier synchronization, costas ring, based on Verilog carrier synchronization ring )

verilog实现的LMS的算法，另外有tb文件可以测试已测试代码正确……(verilog implementation of LMS algorithm, another tb files can test the code has been tested properly ......)