用FPGA verilog hdl实现千兆以太网MAC。

JESD204协议简单透彻的讲解，对做高速AD的朋友有一定的帮助(Understanding control characters in JESD204)

采用FPGA 来实现一个基于OFDM 技术 的通信系统中的基带数据处理部分，即调制解调器。其中发射部分的调制 器包括：信道编码（Reed-Solomon 编码），交织，星座映射，FFT 和插 入循环前缀等模块。(FPGA to implement a baseband data based on OFDM technology in the communication system processing section, namely modem. Transmitter modulator includes: channel coding (Reed-Solomon coding), interleaving, constellation mapping, FFT and insert the cyclic prefix modules.)

verilog实现的“并行输入、并行输出移位寄存器”-verilog to achieve a " parallel input, parallel output shift register"

基于USART的ARM与FPGA通信实验(Based on the ARM and FPGA communication experiment of USART )

vhdl编写的硬件乘法器-prepared by the VHDL hardware multiplier

主要是基于FPGA(EP2C8Q208I8)下的SRAM驱动，SRAM型号为IS61LV25616，程序语言为Verilog,开发环境为quartusII 7.0,为一工程，可直接下载到FPGA中，含电路图(Mainly based on FPGA (EP2C8Q208I8) driving under the SRAM, SRAM model IS61LV25616, programming language for Verilog, a development environment for quartusII 7.0, for a project, can be downloaded directly to the FPGA, including circuit diagrams)

这是spi接口传输的一部分内容，本源码一共三部分，功能：spi接口的的实现即对外设的读写数据-This is the spi interface transfer part of the contents of a total of three parts of this source, function: spi interface that the realization of the read and write data to the peripheral

用VHDL写的源代码程序，包涵三人表决器，七人表决器，全加器以及模24，模60的计数器，都是单文件的，由于程序小又多，所以集中在一起，供新学习VHDL语言的朋友们参考。-With VHDL source code written procedures, includes three of the voting machine, vote on seven people, and full adder, as well as modulus 24, modulus 60 counters, are single-file, as many small procedures, so together for the new Learning VHDL Language Reference friends.

人的移动的跟踪，VERILOG实现，能跟踪人的画面移动(Tracking the movement of people, VERILOG realize that can track the person)

基于verilog的DDS设计,内附代码,仿真环境等说明(the DDS design based on verilog)