用FPGA verilog hdl实现千兆以太网MAC。

Bone microphnoe simulator. this is a trial to de-noise the bone microphone signals. This also utilizes om-lsa algorithm

xlinx sparten 3E实验板，实现时钟闹钟功能，闹钟播放电子音乐，时钟，闹钟通过LCD屏显示。自己写的，亲测可用。                                                                                                                    

AD9235FPGA编程 可AD采集信号 信号频谱检测 检测任意波形输入(AD9235FPGA programming allows AD to collect signal and spectrum detection and detect arbitrary waveform input.)

I2C接口标准建模源码,I2C interface standard modeling source-I2C interface standard modeling source

二维DCT，FPGA实现JPEG压缩中的二维DCT(dct)

关于基数分频技巧设计,基于VHDL语言,对实际设计有帮助-DIVIDE

说明：  处理器系统，处理器加上存储器，从存储器取出指令放入处理器执行(processor system, instructions stored in ROM, a counter generate address and the processor execute instructions.)

设计的结构是纹波进位加法器架构，但执行的操作是32位加法和32位减法

使用VHDL进行分频器设计，主要是一些分频的东西，整数分频，小数分频，奇次分频和偶次分频-Divider using VHDL to design, mainly because some sub-band stuff, integer divider, fractional-N, odd and even sub-sub-sub-sub-band frequency

Verilog_HDL源码， Verilog_HDL源码-Verilog_HDL source, Verilog_HDL FO