用vhdl语言 来实现 四位并行加法器的功能 是本科生的必学内容...

Xilinx FPGA 时序约束资料，原厂出品，经典不需要理由(Xilinx FPGA timing constraint information, original, classic no reason)

fft变换三个中的一个（站长：三个代码算一个）-one of the three fft transfermation code

uart 收发器 verilog 代码，实现自收发功能 sys clk = 25m, baud 9600 停止位1， 无校验位； 代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过； (verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no parity code from the transceiver features a serial port, and the contents received from the PC will send the PC, another Potter rate, self-modifying code can, in the alter of the FPGA, debugging through )

用vhdl实现24小时计数器，方法简单实用。 仿真环境MAXPLUS--use VHDL to achieve 24-hour counter, simple and practical method. Simulation environment Segments-

FPGA设计攻略及流程，包含时序收敛和引脚约束(FPGA design strategy and process, including time series convergence and pin constraints)

基于DSP28335的产生ADc采样的程序(Program for generating ADC sampling based on DSP28335)

带LDN的的同步的预置数端子，并且带CLR的异步清零端-LDN synchronization with the preset number of terminals, and cleared with CLR Asynchronous client

这个是用VHDL实现FPGA对FLASH的读写。(This is achieved using VHDL FLASH FPGA to read and write.)

verilog实现mp3解码程序，包括testbench(mp3 decoder verilog implementation procedures, including the testbench)

可以实现DDS 的正负线性扫频以及在线参数设置(DDS ad9914/ad9915 code)