-
adrv9009_fmcomms8_sync_test_bash
说明: adrv9009的测试平台的测试脚本,适合新人参考(Adrv9009 test platform test script, suitable for new reference)
- 2020-08-03 08:50:49下载
- 积分:1
-
mux21a
在VHDL结构体中用于描述逻辑功能和电路结构的语句分为顺序语句和并行语句两部分,顺序语句的执行方式十分类似于普通软件语言的程序执行方式,都是按照语句的前后排列方式顺序执行的。(VHDL structure in the body used to describe the logic function and circuit structure of the order of statements and expressions are divided into two parts in parallel statement, modalities for the implementation of the order of statement is very similar to ordinary language software program implementation, are in accordance with the statements before and after the arrangement of the order implementation.)
- 2008-12-24 18:25:20下载
- 积分:1
-
基于VHDL的rsc(7,5)递归卷积编码器
rsc递归卷积编码器是turbo码的分量编码器,递归相对于普通的卷积码多了一个反馈,拥有更好地重量谱分布和更加的误码率特性,且码率越高,信噪比越低其优势越明显。利用D触发器组成的rsc生成器,逻辑思维简单,里面包含有测试波形以及测试的结果
- 2022-06-28 16:38:10下载
- 积分:1
-
jishi
计时器=================(Timer =================)
- 2009-12-27 21:41:10下载
- 积分:1
-
sdram 代码
sdram 代码在最后要强调的是,本专题以技术为主,由于篇幅的原因,不可能从太浅的方面入手,所以仍需要有一定的技术基础作保证,而对内存感兴趣的读者则绝不容错过,这也许是您最好的纠正错误认识的机会!
- 2022-08-23 08:24:46下载
- 积分:1
-
FPGA
基于fpga的多功能电子钟的设计非常使用希望对大家有帮助啊-FPGA-based multi-functional electronic clock design to use would like to help everyone ah
- 2023-06-23 00:15:03下载
- 积分:1
-
EDanDanAssistg
蛋蛋助手,可以动态配置生成代码格式,方便ORM或或程序员的生成工作 ,经测试
(Egg assistant, can be dynamically configured to generate code format, convenient ORM, or programmer generation work, tested)
- 2012-09-10 00:33:07下载
- 积分:1
-
can-lite-vhdl-master
说明: CAN VHDL Code. Behavioral implementation of CAN bus interface.
- 2021-01-19 21:48:41下载
- 积分:1
-
eDP
eDP接口TFT-LCD显示驱动原码(verilog+c)(eDP Interface TFT-LCD display driver source code (verilog+c))
- 2020-10-17 09:17:27下载
- 积分:1
-
用VHDL的玛摩尼的ASIC设计
ASIC Design using VHDL by Shyam Mani
- 2022-02-21 17:12:20下载
- 积分:1