基于VHDL可编程BPSk调制教学~~~十分好用`~容易学会

mux one hwich is teh best knwo progerma i n the workdl and ist is the

基于verilog的2FSK调制程序，simulink仿真通过(2FSK modulation program based on Verilog, Simulink simulation passed)

配置GTH ip的例子工程，选用7 series 芯片的GTH 113quad的四个通道，在程序中每个链路利用自己的恢复时钟进行数据解码，所以四个通道可以各自独立运行；成功工作在2.54Gb/s的链路状态，长时间（>24小时）的测试，误码率一直为0.(The GTH ip example project is configured with four channels of the GTH 113quad of the 7 series chip. Each link in the program uses its own recovery clock for data decoding, so the four channels can operate independently; the successful operation is at 2.54Gb/ The link state of s, long time (>24 hours) test, the bit error rate has been 0.)

说明：  实现主干道交通灯显示，以状态机程序实现，并用数码管进行红绿灯倒计时的显示，内置计数模块，交通灯控制模块，数码管显示模块，并对各模块用电路图的方式进行连接。对于学习VHDL语言有所帮助。(The main road traffic light display is realized by the state machine program, and the digital tube is used to display the traffic light countdown. The counting module, the traffic light control module and the digital tube display module are built in, and each module is connected by the circuit diagram. It is helpful for learning VHDL.)

Verilog版的C51核(OC8051)-Verilog version of the C51 core (OC8051)

verilog编写的16阶升余弦滤波器 采用直接型结构实现 对方波进行滤波 输出波形 含testbench文件(order raised cosine filter verilog written 16 direct-type structure to achieve the other wave filtering the output waveform containing testbench file)

带自适应波特率发生器UART实现，经过FPGA验证的！-UART baud rate generator with adaptive realization, after FPGA validation!

完成ITUR656标准的视频流数据向RGB格式的转换。-Complete video streaming ITUR656 standard data format to RGB conversion. Test module

线性伸展TDC的verilog，包含门级网表(TDC linear stretch of verilog, includes gate-level netlist)

cordic算法的verilog 语言实现，注释详细，资料齐全，实现了cordic算法的各个功能，可以计算正余弦(cordic algorithm verilog language, detailed notes, and complete information)