vhdl经典源代码――时钟设计，入门者必须掌握

XAPP224 VHDL Data Recovery design file

Z源逆变器简单升压模拟仿真。调制方式为SPWM，通过设置三角波幅值和比较电压，即可调节输出电压。(Z-source inverter simple step-up simulation. Modulation mode SPWM, by setting the the triangle amplitude and the comparison voltage to regulate the output voltage.)

German REAL LPT! USB2LPT

花了半个月才改好的Atera DE1/DE2 ps2 IP 驱动核。放在FPGA工程目录下可以直接使用。本IP能够驱动PS/2键盘和鼠标。使用时只要调用HAL目录下的文件即可以直接使用！-Spent a good two weeks we have made some changes Atera DE1/DE2 ps2 IP-driven nuclear. On the FPGA project directory can be used directly. The IP to drive PS/2 keyboard and mouse. When used as long as the call HAL directory file that can be used directly!

数字逻辑与系统的关于所有的器件74LS的介绍，功能表(Digital Logic and System devices 74LS on the introduction of all the menu)

基于FPGA的SD卡音频播放器 经过调试可以直接用，音质很好有MP3的所有功能(FPGA-based audio player, SD card can be directly used after debugging, good sound quality with all the features of MP3)

一个任意整数分频程序,采用VHDL语言编写，编译通过-An arbitrary integer frequency procedure for the VHDL language, the compiler through

利用verilog HDL逐点比较法实现直线和圆弧插补(Use verilog HDL by-point comparison method to achieve linear and circular interpolation)

UART的完整发送程序，包括完整的工程核源代码。-UART to send the complete procedure, including the complete source code of nuclear engineering.

FPGA VERILOG 用DCFIFO实现 跨时钟域的数据传输，已验证，直接可用-FPGA VERILOG using DCFIFO realize cross-clock domain data transfer, has been verified, directly available