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一个8位CISC结构的精简CPU,2还提供了编译器
一个8位CISC结构的精简CPU,2还提供了编译器-an eight streamline the structure of the CISC CPU, the two also provided compiler
- 2022-02-28 11:37:41下载
- 积分:1
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I2C_read
说明: I2C读程序,通过状态机描叙,仿真达到要求(I2C Reading, depicts through the state machine, called Simulation)
- 2006-04-07 15:51:19下载
- 积分:1
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float_multi
说明: FPGA Verilog浮点数乘法运算,采用单精度浮点型小数格式,运算结果精度可设置,可封装成IP核(FPGA Verilog floating-point multi operation, using single precision floating-point decimal format, the accuracy of the operation results can be set, can be packaged into IP core)
- 2020-07-02 01:20:01下载
- 积分:1
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The use of Altera' s FPGA
使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上用硬件描述语言实现一个ROM存储器。-The use of Altera" s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware description language to achieve a ROM memory.
- 2022-08-23 17:16:15下载
- 积分:1
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DE2_CCD
说明: 此程序用来实现图像的采集和帧数的计算功能。(Image acquisition and calculation of the number of frames.)
- 2011-04-17 09:43:37下载
- 积分:1
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全数字fsk调制解调的实现 verilog源码
全数字fsk调制解调的实现 verilog源码-All-digital realization of fsk modem verilog source code
- 2023-04-11 15:55:04下载
- 积分:1
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四进制计数器模块,使用VHDL语言编写,在ISE8.1中经过测试的模型...
四进制计数器模块,使用VHDL语言编写,在ISE8.1中经过测试的模型-quaternary counter module, the use of VHDL language, in which ISE8.1 tested model
- 2022-02-06 20:22:16下载
- 积分:1
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It is then register ( shifter) PISO ( Parallel
It is then register ( shifter) PISO ( Parallel - in, serial - out)-It is then register ( shifter) PISO ( Parallel- in, serial- out)
- 2022-03-14 08:29:42下载
- 积分:1
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它执行浮点运算单元
it performs the floating point arithmetic unit
- 2022-08-09 12:14:10下载
- 积分:1
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shumagua
通过数码管和单片机的组合 制作成的数码管时钟程序(Through the combination of digital control and made into a single-chip digital clock program)
- 2013-10-27 12:30:04下载
- 积分:1