Xilinx FPGA RAM块可通过JTAG

黑金开发板对时钟信号的编写实验以及调试，相关代码如压缩包所示(CLOCK FPGA)

verilog 键盘输入程序，用于led灯的显示-Verilog keyboard input program for led lights display

 采用quartusⅡ仿真软件实现多功能信号发生器的FPGA设计,当输入端有时钟信号输入时，各个信号发生器模块独立运行，独立存在，发出各种信号，这些信号作为数据选择器的输入信号，在数据选择器的作用下，波形切换到相应的模块输出，将通过示波器显示出相应的波形图。

波形发生器，带TESTBENCH， 多平台 -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn -waveform generator, with TESTBENCH. Multi-platform-- the design makes use of the new shift opera tors available in the VHDL-93 std-- this design passes the Synplify synthesis check-- downloa d from : www.fpga.com.cn

512×8bid的FIFO 含工程文件，基于QUARTUs-512 × 8bid the FIFO with the project document, based on the QUARTUsII

LTE is an abbreviation for Long Term Evolution.

FPGA开发,DE2开发板上实现,从SD卡读出MP3文件并播放,(即是开发一个简单的MP3播放器)(FPGA development, DE2 development board realize, from the SD card to read out and play MP3 files, (that is, the development of a simple MP3 player))

TIMING LEARNING -TIMING LEARNING

CY7C63723 功能及其引脚描述，外围电路和仿真数据(The CY7C637 is an 8-bit RISC OTP microcontroller.)

用verilog写的简单的CPU，有详细注释(Use verilog to write a simple CPU, with detailed notes)