Xilinx FPGA RAM块可通过JTAG

本文为verilog的源代码-In this paper, the source code for Verilog

基于软输出固定复杂度球形译码的高效迭代检测算法，最新的球形译码论文(Iterative detection algorithm based on a fixed complexity soft-output sphere decoding efficiency, sphere decoding papers)

现在最流行的RTL设计方法之一，本书为全球流行的设计入门书籍(One of the most popular RTL design methods nowadays, this book is an introductory book for popular design all over the world.)

this contain the source code for noise cancellation ,which can be used in c platform.

步进电机定位控制系统，VHDL程序，里面有注释(Stepper motor position control system, VHDL program, there are comments)

this project is about FIR FIlter By VHdl codes in the ISE.

秒表 东北大学秦皇岛分校 电子设计自动化 实验(Stopwatch Northeastern University at Qinhuangdao electronic design automation experiment)

串行流水线格式:使用COrdic 算法计算反正切:向量模式下求角度 16bit :数据全部补码格式 (Serial line format: Use COrdic algorithm arctangent: seeking angle vector mode 16bit: full complement data format)

用verilog实现的buffer，经过了fpga平台验证。(Implement buffer with verilog.)

可YCrCb2RGB集成模块（Verilog）采用三行，它们简单的做分数运算，有流水线技术