Xilinx FPGA RAM块可通过JTAG

EAB_VHDL

用max+plusII编写的vhdl程序 乒乓球游戏机-with max plusII vhdl procedures for the preparation of the table tennis game

用AHDL语言编写,MAXPULS开发.通信不受外部时钟速率和数据字节数目限制.-with AHDL prepared MAXPULS development. Communications from external clock rate and restriction on the number of data bytes.

说明：  彩条产生程序。。。。720p需添加74.25M时钟(colorbar generation. need 74.25mhz clock if 720p gen)

主要介绍了关于MAGIC3000系列CPLD开发板的十个实例,如霓虹灯演示、与PC串口通信等。-Mainly on the introduction MAGIC3000 series CPLD development board of the 10 examples, such as neon demonstration, with the PC serial port communications.

本程序采用VHDL语言设计了虚拟电子琴。电子琴的设计包括四个模块：弹奏模块keyplay、自动演奏模块autoplay、查表及显示模块table和分频模块fenpin。 弹奏模块keyplay根据按键动作 请点击左侧文件开始预览 ！预览只提供20%的代码片段，完整代码需下载后查看 加载中 侵权举报

异步的fifo,写时钟和读时钟相互独立，能够对数据进行缓存处理。希望对大家有用(Asynchronous fifo, write clock and the read clock independent of each other, capable of processing the data cache. I hope useful)

基于CPLD 的光电脉冲码盘 信号四倍频电路设计-CPLD-based electro-optical pulse encoder signals four multiplier circuit design

FPGA控制m25p16flash芯片读写控制spi协议 可实现擦除写入读出功能(SPI protocol for read and write control of m25p16 flash chip controlled by FPGA Erase Write-Read Function)

一个高级培训班的内部资料,非常宝贵,读者可以掌握FPGA的基本思路-A high-level training of internal information, are very valuable, readers can grasp the basic ideas FPGA