利用VHDL实现CPLD（EPM240T100C5）的串口发送程序

This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.

freeDev数字应用开发板中的VGA控制器的IP核的verilog实现-freeDev digital application development board of the VGA controller IP core implementation of the verilog

1553B的编解码程序很好用给大家分享 -the series 1553B decoder procedure is useful for everyone to share share

UART program for fun(UART)

FPGA上使用硬件描述语言实现俄罗斯方块游戏，该游戏支持PS2键盘输入，VGA视频输出，游戏可以选择不同的难度，同时可以记录显示游戏得分，同时包含VC上位机方块形状编辑器的一整套项目方案

xilinx CTC IPcore(encoder 和 decoder)的测试，经过AWGN信道。 -This simulation uses a AWGN module to include noise as part of the simulation. Prior to running the simulation, the UniSim models for the encoder and decoder must be generated as well as the AWGN module.

基于VHDL的数字计时器，手动可控正计时和倒计时(含复位键和使能键)(VHDL-based digital timer and countdown timer being controlled manually (with the reset button and enable key))

一个小程序,弹跳消除电路,可消除按健的毛刺干扰-a small procedure, bouncing elimination circuit, according to remove the burr-interference

本程序实现流水线功能，您可根据自己需要更改参数，试用芯片xilinx，用verilog语言编写(This program implements the pipeline, you may be required to change the parameters according to their own try xilinx chip with verilog language)

vhdl,序列信号检测模块，此模块检测1110010，可改为任意序列，输出电位为1为检测出，否则为0-vhdl, sequence of signal detection module, this module testing 1.11001 million, can be changed to an arbitrary sequence, the output potential of an as detected, otherwise 0