verilog hdl verilog hdl verilog hdl

卷积码编码译码程序以及其modelsim仿真波形文件等(Convolutional code encoding and decoding procedures and the Modelsim simulation waveform file)

TI公司的DAC5578驱动程序，经测试过的，CSDN资源分享(DAC5578 Driver of TI Company Tested and CSDN Resource Sharing)

串口中断＿niosII.rar 解压密码：www.21control.com

模拟示波器的现实程序，有x，y和光标。采用AD5440输出，现实效果很好。（示波器x-y方式）(Analog oscilloscope reality program, there are x, y and cursor. Using AD5440 output, real good results. (Xy oscilloscope mode))

数字钟通过verilog实现，并且支持Modelsim仿真(The digital clock is implemented by Verilog and supports Modelsim simulation)

台湾IC中心VHDL讲义，内容详细，适合IC前端设计参考(Taiwan s IC Center VHDL handouts, detailed reference design for front-end IC)

Paint for SPARTAN 3E

特权同学主讲的FPGA设计的时序约束专题（STA部分）(Speaker privileged classmates timing constraints for FPGA design topics (STA section))

A complete VHDL source code to 5-storey elevator

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