io 组件，用vhdl实现io端口的控制，包括输入输出，握手信号，...

该程序用来实现电话计时以算取费用，比较简单(telephone cost metering verilog code)

说明：  ask psk 编码调制的vhdl 实现(ask psk coded modulation to achieve the VHDL)

FPGA代码，包含地址译码模块、16位锁存器、AD片选、死区及滤除窄脉冲、过流和短路保护、解除脉冲封锁模块、PWM模块、PWM选择 (FPGA code, including the address decoder module 16 latches, AD chip select, filter out the dead and narrow pulse, overcurrent and short circuit protection, lifting the blockade pulse module, PWM module, PWM selection)

FPGA设计软件的绝佳入门书籍，本人珍藏，全部吐血奉献之2，请大家赶紧下！-FPGA design software, an excellent entry-books, I treasure all the blood sacrifice of 2, please hurry under the U.S.!

最终FFT 64点使用定点。

加法计数器的VHDL工程，程序，仿真图形-adder jishuqi de VHDL FANGZHEN ,CHENGXU

该书介绍了英特尔的80x86CPU和一些串行通信芯片，以及汇编语言。(The book introduces the Intel 80x86CPU and some serial communications chip, and assembly language.)

坦克大战的演示程序 ，实现了基本的人机交互-Battle City demonstration program to achieve the basic human-computer interaction

SDRAM控制器源码，内含完整的控制器verilog源代码和测试代码，超值哈。(This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1.)

Verilog OTP ROM source code