FPGA设计软件的绝佳入门书籍，本人珍藏，全部吐血奉献之2，请大家赶紧下！...

verilog实现的简易通用型CPI接口-verilog easy to achieve CPI general-purpose interface

Cadence的VHDL运算库包，实现求方根，平方你是不是以前不知道怎么弄．哈哈．-Cadence VHDL Operational the package, seeking to achieve root, You are not square did not know how get. Ha ha.

51数字钟带各种扩展年，月，日等并且可预置。用汇编语言写的(51 digital clock with extended assembly language)

51单片机的下载器PCB图，可以用于at89cXX和at89c0xx系列的单片机的程序烧录，简单好用！使用proteus画的板。(51 MCU PCB map downloader, can be used at89cXX and procedures for microcontroller series at89c0xx burning, easy to use! Drawing board with proteus.)

一个实用的uart协议模块，使用verilog 实现(A practical uart protocol modules, use verilog to achieve)

本程序为四路抢答器verlog HDL语言工程实例。(This program is four Responder verlog HDL language engineering examples.)

OFDM modulation source code written in Matlab

DDR2 SDRAM仿真模型，适合于ModelSim下工作，请先阅读readme-DDR2 SDRAM Simulation Model which is suitable for modelsim. Please read readme file firstly.

The VHDL Cookbook First Edition July, 1990 Peter J. Ashenden Dept. Computer Science University of Adelaide South Australia

利用matlab设计了一个切比雪夫滤波器，并且对滤波器性能进行了仿真分析。(Using the matlab design a chebyshev filter, and has carried on the simulation analysis on filter performance. )