protel fpga library a popular package is very difficult to find the

使用verilog写的频率计，可切换档位(Frequency counter using verilog write switch stalls)

这是本人自己编写的可用于256*256大小的图像进行sobel边缘检测的vhd文件，可在QuartusII或MaxplisII下综合和仿真，并在FPGA上测试过。可以进行修改支持其他大小图像的sobel边缘检测，同时还可以实现其它的图像模块化处理算法，例如高斯滤波，平滑等。(this is my own preparation for the 256* 256 size of the image segmentation Edge Detection vhd document in the next QuartusII or MaxplisII integrated and simulation, and the FPGA tested. Can be adapted to support other size image segmentation edge detection, It can also achieve other modular image processing algorithms, such as Gaussian filtering, smoothing and so on.)

说明：  OFDM的简易verilog仿真程序，环境是quartus，版本需要7.2以上(OFDM Modulation and Demodulation using Verilog in Quartus)

基于FPGA的数字电压表 两种方案 一种VHDL一种Verilog(Digital voltmeter based on FPGA)

LVDS的应用的Verilog HDL例子程序(LVDS example of the application procedures for the Verilog HDL)

实施软件定义无线电的关键第一步是向与数字到模拟控制器接口。好花费的时间是在这工作，因为驾驶 DAC 的信号的时间必须是正确的设备才能正常工作。Spartan3e 培训师局是有 LTC2624 DAC 连接到通过 SPI 总线 FPGA。用于进行通信的 DAC 的信号是 SPI_MOSI、 DAC_CS、 SPI_SCK、 DAC_CLR。下表中描述的接口信号。

HDLC通信协议，FPGA实现，包含源文件和仿真测试文件。(HDLC comunication)

说明：  FPGA应用状态机版，适合初学者学习状态机三段式，ASMD图的理解和翻译，以及Verilog语言的应用 最后对仿真的一些理解 其中包含HDL设计及testbench描述 根据要求设计了一个能求出一个32bit字中两个相邻0之间最大间隙的电路。(FPGA application state machine version, suitable for beginners to learn state machine three-stage, ASMD chart understanding and translation, and Verilog language application. Finally, some understanding of simulation, including HDL design and testbench description According to the requirements, a circuit is designed to find the maximum gap between two adjacent zeros in a 32 bit word.)

Complex of three-point Gauss-lengend the Formula pi, Including orbital maneuvering simulation, initial orbit calculation, University of numerical analysis algorithms.

说明：  SJA1000的ip核和相关测试脚本,OPENCORES 下载(SJA1000 IP downloads from opencores)