VHDL学习手册

由VHDL 语言实现的数控分频 利用的是QUARTUES环境已经得到验证-By the NC VHDL language is the use of sub-frequency QUARTUES environment has been tested

采用双线性变换法设计IIR数字滤波器设计的c代码，包括低通、高通和带通(Document recording the design of IIR digital filter c code)

Array muiltiplier verilog code.. 4 bit two inputs with 8 bit outputs

RS（255，223）编码器，已实际运用到产品中(RS (255,223) encoder has actually applied to products)

本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设 计，包括偶数分频、非 50％占空比和 50％占空比的奇数分频、半整数 （N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可 通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合，形成可使 用的电路，并在 ModelSim 上进行验证。 -This article describes the use of examples in the FPGA/CPLD prescaler to use VHDL to design, including the even-numbered sub-frequency, non-50 duty cycle and 50 duty cycle of the odd-numbered sub-frequency, semi-integer (N+ 0.5) sub-frequency, fractional-N, as well as scores of sub-band frequency points. All can realize through the Synplify Pro or FPGA manufacturers integrated synthesizer to form a circuit can be used and verified in the ModelSim on.

Xapp 200 64 bit DDR SDRAM design files for Xilinx Vertix

千兆以太网设计，包括组包解包，可以实现大数据传输功能。(Unpack the gigabit Ethernet is designed, including group package, can realize large data transfer function.)

用来实现IRIG_B码的解码程序，在XILINX ISE上运行过没有问题，(Used to achieve IRIG_B code decoding process, in XILINX ISE run-off is no problem,)

ofdm的发射链路和接收链路的Verilog源代码，包括长短训练序列的生成，导频插入，加cp，ifft。(Source code of transmission link and reception link of OFDM)

用32位NiosII处理器实现RS232通信，可以给初学者一个借鉴。-NiosII with 32-bit processors to achieve RS232 communication, can give a reference for beginners.