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VHDL学习手册

于 2022-06-12 发布 文件大小:5.21 MB
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VHDL学习手册-VHDL study manual

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  • FPGA_Seg7_dsp
    关于VHDL和verilog的数码管显示程序,写的很好,值得参考。(About VHDL and verilog digital tube display program, write well, worth considering.)
    2014-08-01 11:00:51下载
    积分:1
  • dds_ok1
    说明:  基于FPGA的信号发生器,产生了正弦波,方波,锯齿波和三角波四种波形,按下一次按钮,波形切换一次。按下另一个按钮,改变波形的频率(The signal generator based on FPGA can generate four kinds of waveforms: sine wave, square wave, sawtooth wave and triangle wave. Press the button once and switch the waveform once. Press another button to change the frequency of the waveform)
    2020-09-16 18:30:37下载
    积分:1
  • 39736216MyDspToolbox
    使用Matlab Gui实现的数字信号处理常用算法,包括卷积,FFT,FIRIIR数字滤波器设计,最佳滤波器,自适应滤波,卡尔曼滤波等
    2012-05-01 11:59:57下载
    积分:1
  • ofdm_modulation
    OFDM modulation source code written in Matlab
    2009-06-01 17:52:44下载
    积分:1
  • svtb_ahb_sram
    说明:  一款verilog设计的SRAM控制器,可以实现AHB总线控制的功能。(abcdefghijklmnopqrstuvwxyz)
    2020-06-30 13:40:02下载
    积分:1
  • 串uart的vhdl,verilog,lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)uart 源码 (Veri...
    串uart的vhdl,verilog,lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)uart 源码 (Verilog)uart 源码 (VHDL)uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) uart source (Verilog) uart source (VHDL) uart16550.tar
    2022-04-12 23:45:53下载
    积分:1
  • 50 cases of practical CPLD design, very classic CPLD design, including 50 typica...
    CPLD实用设计50例,非常经典的CPLD设计,包含50个实际的典型应用,涉及直流电机PWM驱动,编码等内容,有了这50例,举一反三,就会了很多应用-50 cases of practical CPLD design, very classic CPLD design, including 50 typical practical applications, involving PWM DC motor driver, coding, etc., with these 50 cases, giving top priority will be a lot of applications
    2022-02-25 20:47:07下载
    积分:1
  • Verilog-design-and-identify-book
    找到这本书的完整版了。呵呵,贴出来和大家共享。这是本好书,我买了一本作为Verilog的参考书。这本书语法部分集中,便于查阅,此外讲了很多实用的设计思想。最重要的是本书薄,可以完整看完。强烈推荐。 (如果只是查阅,电子版就可以,如要完整学习,建议还是买纸质版的)(Find the full version of this book. I posted and share. This is a good book, I bought a reference book as Verilog. Syntax in this book section focuses on ease of reference, in addition to speaking a lot of useful design ideas. The most important thing is that the book is thin, you can complete reading. Highly recommended. (If you only access the electronic version to complete learning, suggestions or to buy the paper version))
    2012-06-07 21:58:19下载
    积分:1
  • the_last
    VHDL语言实现两个人掷骰子游戏,最多6次,大者胜则结束游戏并在点阵上显示,一直平手则一直进行直到达到6次。(Achieving the dice game between two people by using VHDL language.The maximum number of times is 6.The game will over when there is a biger one in one time,otherwise,the game will continue until the time of the game is up to 6.)
    2021-01-21 12:18:42下载
    积分:1
  • Implement the 7 segment diplay on spartan 3
    Implement the 7 segment diplay on spartan 3
    2022-02-10 04:28:00下载
    积分:1
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