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FPGA控制AD逐点采集信号,并将AD转换后的数据串行发送出去。
FPGA控制AD逐点采集信号,并将AD转换后的数据串行发送出去。-FPGA to control the signal sampling point by point AD, AD conversion and serial data sent.
- 2023-05-07 13:55:03下载
- 积分:1
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680605rece_7E
hdlc协议的相关程序,用verilog语言编写,供大家交流学习(hdlc protocol procedures using Verilog language for the exchange of learning)
- 2013-01-18 00:53:58下载
- 积分:1
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5
说明: 用VHDL语言实现电子钟(Using VHDL language electronic bell)
- 2008-11-28 21:20:23下载
- 积分:1
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StopWatch
This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.
- 2013-10-04 00:53:49下载
- 积分:1
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newViterbi217
基于IEEE802.11n标准,采用verilog语言设计的(2,1,7)卷积码viterbi译码器,支持1/2,2/3,3/4,5/6四种码率的译码,以测试无误(IEEE802.11n standard Verilog language design (2,1,7) convolutional code viterbi decoder support 1/2, 2/3, 3/4, 5/6 four bit rate decoding to test and correct)
- 2020-06-29 08:40:01下载
- 积分:1
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VendingMachine
VHDL Vendingmachine source
- 2013-11-02 06:19:46下载
- 积分:1
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A4_Led3
说明: led学习控制l44444444444444(led verilog led ccccccc)
- 2019-05-06 09:38:14下载
- 积分:1
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EDA-traffic-lights-control-system
EDA的交通信号灯的控制系统的程序,设计一个交通信号灯控制器,由一条主干道和一条支干道汇合成十字路口,在每个入口处设置红、绿、黄三色信号灯,红灯亮禁止通行,绿灯亮允许通行,黄灯亮则给行驶中的车辆有时间停在禁行线外。(EDA traffic lights control system procedures)
- 2013-04-18 20:09:42下载
- 积分:1
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pll
用FPGA实现数字锁相环,开发环境为ISE(Using FPGA digital phase-locked loop, development environment for ISE)
- 2021-03-19 18:29:19下载
- 积分:1
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M4A564/32 CPLD VHDLA程序,调试可用,51扩展.
M4A564/32 CPLD VHDLA程序,调试可用,51扩展.-M4A564/32 CPLD VHDLA procedures, debugging is available, 51 to expand.
- 2023-08-25 16:25:03下载
- 积分:1