用VHDL语言编程完成数码管0

vhdl,序列信号检测模块，此模块检测1110010，可改为任意序列，输出电位为1为检测出，否则为0-vhdl, sequence of signal detection module, this module testing 1.11001 million, can be changed to an arbitrary sequence, the output potential of an as detected, otherwise 0

2. You may use this core in any way, be it academic, commercial, or -- military. Modified or not.-2. You may use this core in any way, be it academic, commercial, or-- military. Modified or not.

并口通讯代码 并口通讯代码（调试通过） --该代码目前能实现单个字节的收发-Parallel communications code (debugging through)-- The code can now achieve a single byte of Transceivers

一个可综合的同步FIFO的verilog源代码-An integrated synchronous FIFO in Verilog source code

说明：  fpga的RS485代码,非常容易，适合学习(the code of rs485 in fpga, very easy,suitable for learning)

调整iq幅度不平衡的模块，可以解决载漏和边带问题。(Iq amplitude imbalance adjustment module can be resolved carrier and sideband leakage problems.)

VHDL上机手册（基于Xilinx ISE） ___________________________________________________ 1 ISE 软件的运行 2 创建一个新工程 3 创建一个VHDL源文件框架 4 输入VHDL程序 *5 仿真 6 创建Testbench波形源文件 7 设置输入仿真波形 -eda

本代码实现了486总线的功能，初学者可以借鉴学习-This code implements the 486 bus functions, beginners can learn to learn

is61lv25616简单的verilog程序，完成sram读写(is61lv25616 simple verilog program, complete sram read and write)

LTE is an abbreviation for Long Term Evolution.