Verilog digital system design tutorials, e

1024点fft verilog hdl-1024-point fft verilog hdl

crc循环冗余校验码，用于对传输信号进行编码校验，是信息更可靠-crc cyclic redundancy check code used to transmit coded signals to verify, the information is more reliable

sdram 代码在最后要强调的是，本专题以技术为主，由于篇幅的原因，不可能从太浅的方面入手，所以仍需要有一定的技术基础作保证，而对内存感兴趣的读者则绝不容错过，这也许是您最好的纠正错误认识的机会！

用FPGA实现数字锁相环，开发环境为ISE-Using FPGA digital phase-locked loop, development environment for ISE

USB3.0开发板资料，采用CYUSB3.0(USB3.0 development board, using CYUSB3.0)

掌握二-十进制(BCD码)异步计数器的工作原理和设计方法； 掌握中规模集成二-五-十进制异步计数器74LS90的功能及其应用；(Master II- Decimal (BCD code) the principle and an asynchronous counter design grasp the scale of integration in two- five- Decimal asynchronous counter 74LS90 features and applications )

说明：  there's a clock divider for DE2 altra board clock (50MHz)

UART 源码 (lattice version)-UART source (lattice version)

说明：  此程序为调试通过的程序，带有I2C总线功能的程序.(this procedure through the debugging process, with I2C bus function procedures.)

在汉明码调试中实现了纠错原理，达到更快的效果，更少的资源浪费