串uart的vhdl，verilog，lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)uart 源码 (Veri...

1。源文件保存在src目录，QII的工程文件保存在Proj目录； 2。程序实现的功能是在VGA显示器上显示彩色条纹，共8种颜色， 可以使用嵌入式逻辑分析仪观测信号； 3。modelsim仿真文件在proj--simulation--modelsim中(1. The source file is saved in the src directory QII project file is saved in the directory Proj 2. The functionality of the program is displayed on a VGA monitor color stripes, 8 colors, you can use the embedded logic analyzer observed signals 3. the modelsim simulation files in the proj- simulation- modelsim)

特权同学主讲的FPGA设计的时序约束专题（STA部分）(Speaker privileged classmates timing constraints for FPGA design topics (STA section))

modelsim的一个非常好的教程，有程序源码，PPT，word教程-ModelSim

边界扫描技术相关资料，含各个模块的介绍。很有参考价值。(JTAG TAG CONTROLLER)

verilog alu 8bit for engineers

基于FPGA的1602时钟显示,驱动1602显示时钟,矩阵键盘调时(1602 FPGA-based clock display, clock display driver 1602, when the transfer matrix keyboard)

说明：  ask psk 编码调制的vhdl 实现(ask psk coded modulation to achieve the VHDL)

4X4keypad的防抖动模块，用于假按键的检测-4X4keypad shake the module, the keys for false detection

4 bit convoltion with vhdl.

this is a verilog code of true random number generator using butterfly puf