基于fpga的出租车计费系统，采用自顶向下的设计方法

access must be conf urr arr

SAA7113 ＦＰＧＡ开发实例，非常经典(The SAA7113 FPGA development examples, very classic)

设计一个可容纳四组参赛的数字式抢答器，每组设一个按钮供抢答使用。抢答器具有第一信号鉴别和锁存功能，使除第一抢答者外的按钮不起作用；设置一个主持人“复位”按钮，主持人复位后，开始抢答，第一答对一次加1分，答错一次减1分

四选一编程语言，可以自动生成四选一器件。-First elected four programming languages, you can automatically generate a four selected devices.

VHDL的寄存器读写参考，可自己根据要求重新修改，本示范只做参考用-Register read and write VHDL reference to their request to amend in accordance with, the reference model only

多通道连续声发射数据采集，每个通道最大5M，采用verilog编程，内部用状态机。(Multichannel continuous acoustic emission data acquisition, each channel up to 5M, using Verilog programming, internal state machine.)

10进制计数器，VHDL描述的，实验必备-10 hexadecimal counters, VHDL description of the experiment must

verilog，FPGA的TDC电路设计(verilog ，TDC base on FPGA)

MATLAB辅助设计数字滤波器源代码，QUATUS II 实现！(MATLAB-aided design of digital filter source code, QUATUS II implementation!)

用Verlog HDL编写的数字钟程序，包含时，分，秒，进位，解码，扫描显示等功能。-Written by Verlog HDL ，a digital clock program, including hours, minutes, seconds, into the place, decoding, scanning display.