基于fpga的出租车计费系统，采用自顶向下的设计方法

FPGA编程，经过团体奋战完成，全是底层的IIc和sci通信，完整版。(FPGA programming, after groups fight to the finish, all underlying SCI and IIc communication, full version)

这是一个用VHDL语言描述的I2C自动配置模块，使用了来自opencores.org的I2C核，已在altera的cyclone芯片上调试通过-This is a VHDL language used to describe auto-configuration of the I2C module, the use of the I2C from opencores.org nucleus, the cyclone in the altera-chip debugging through

AGC(自动增益放大) Verilog代码 设计可以参考 第二部分(AGC (automatic gain control) can refer to the Verilog code design )

FFT程序，此程序虽然耗逻辑资源很大，但是在接受数据后的第7个时钟沿就可以输出FFT变换后的数据，对要求时延较低的系统可以考虑-FFT procedure, this procedure should not consume a lot of logic resources, but the data in the first seven clock can be output along the FFT transformed data, the requirements of time-delay system can be considered lower

代码文件夹： ARVI_FSM.v为顶层文件，用于模拟时用。 dataHex.dat 为模拟输入文件（只有10行，象征的意思。实际我们模拟时，dataHex.dat文件足有1个多GB） dataFormat.dat为输入文件对应的带格式的文件 使用modelsim模拟时，将dataHex.dat名字改为CPUContext.txt 结果: result.txt (Code folder: ARVI_FSM.v for top-level documents used for the simulation. dataHex.dat for analog input files (only 10 line, the meaning of the symbol. actual simulation we, dataHex.dat documents have more than one full GB) dataFormat.dat for the input file the corresponding file with modelsim simulation used to dataHex.dat name to CPUContext.txt results: result.txt)

一个时钟程序，还有跑表，感觉相当不错的，有需要就下载吧-A clock procedures, as well as stopwatch, I feel pretty good, there is a need to download it

对pci9054芯片的配置进行了设置，并对PCI9054的各状态机进行了设置，程序经过了测试(Pci9054 chip on the configuration of the set, and each state machine PCI9054 been set, the program have been tested)

GMSK的调制解调，理理想信道，画出其功率谱。 (GMSK modulation and demodulation, management ideal channel, to draw its power spectrum.)

四位密码锁，移位显示，可以设置和更改密码。-4 lock, shift, it can be set up and change your password.

此源代码是基于Verilog语言的持续赋值方式定义的 2 选 1 多路选择器 、阻塞赋值方式定义的 2 选 1 多路选择器、非阻塞赋值、阻塞赋值、模为 60 的 BCD码加法计数器 、模为 60 的 BCD码加法计数器、BCD码—七段数码管显示译码器、用 casez 描述的数据选择器、隐含锁存器举例 ，特别是模为 60 的 BCD码加法计数器，这是我目前发现的最优源代码，应用于解码器领域。(This source code is based on the Verilog language define the continued assignment of 2-to-1 multiplexer, blocking assignments define the 2-to-1 multiplexer, non-blocking assignments, blocking assignments, module code for the addition of 60 BCD counters, BCD code module for the addition of 60 counters, BCD code- seven-segment LED display decoder, the data described by casez selector, for example hidden latch, in particular, the BCD model code for the addition of 60 counters, this is my found that the best current source code, the decoder used in the field.)