基于fpga的出租车计费系统，采用自顶向下的设计方法

I2C配置tvp5150用VHDL写的 -I2C configuration tvp5150 written using VHDL

存储器控制FPGA程序，包括ram，fifo，sdram，flash等。-FPGA memory control processes, including ram, fifo, sdram, flash and so on.

说明：  一种基于FPGA的调频连续波方位向多通道 FMCW SAR的实时成像信号处理方法及FPGA，包 括：步骤一、计算重构矩阵；步骤二、重构方位向 多通道数据，包括：步骤2 .1、对各个通道的回波 数据沿方位向分别间隔补零，并进行方位向傅里 叶变换；步骤2 .2、将方位向傅里叶变换之后各个 通道方位向相同位置的点组合为一个向量并与 重构矩阵相乘，得到重构完成的方位向数据；(An azimuth multichannel FMCW based on FPGA FMCW SAR real-time imaging signal processing method and FPGA, package Including: Step 1: calculate the reconstruction matrix; step 2: reconstruct the orientation Multichannel data, including: step 2.1, echo of each channel The data is compensated with zero along the azimuth direction respectively, and the azimuth Fourier is carried out Step 2.2, after the azimuth Fourier transform The points of the same position in the channel azimuth are combined into a vector and are connected withThe reconstruction matrix is multiplied to get the reconstructed azimuth data Step 2.3. Repeat step 2.3 for the data of different distance gates)

German REAL LPT! USB2LPT

超級好用 25M~100HZ的除頻器 寫了好久 超級實用 歡迎下載(Super easy to 25M ~ 100HZ of divider wrote a long time super practical welcome to download)

ATSHA204_S加密芯片资料，学习使用该芯片必读资料(ATSHA204_S encryption chip data, required reading for learning to use the chip)

简易数字存储示波器verilog源代码 经过EP2C8Q208C8验证(Simple digital storage oscilloscope verilog source code has been verified EP2C8Q208C8)

IIC控制器 for Sopc Builder-IIC controller for Sopc Builder

彩条产生程序。。。。720p需添加74.25M时钟(colorbar generation. need 74.25mhz clock if 720p gen)

完成RS（5，3）编码程序，运用Verilog语言。(Complete the RS (5,3) coding process, the use of Verilog language.)