基于fpga的出租车计费系统，采用自顶向下的设计方法

这是本人自己编写的可用于256*256大小的图像进行sobel边缘检测的vhd文件，可在QuartusII或MaxplisII下综合和仿真，并在FPGA上测试过。可以进行修改支持其他大小图像的sobel边缘检测，同时还可以实现其它的图像模块化处理算法，例如高斯滤波，平滑等。(this is my own preparation for the 256* 256 size of the image segmentation Edge Detection vhd document in the next QuartusII or MaxplisII integrated and simulation, and the FPGA tested. Can be adapted to support other size image segmentation edge detection, It can also achieve other modular image processing algorithms, such as Gaussian filtering, smoothing and so on.)

vhdl 的testbench编写教程，英文ppt以及源码工程(Write tutorials, as well as English ppt Source of engineering vhdl testbench)

fpga串口收发完整程序，Verilog语言。(FPGA configuration PLL complete program, Verilog language.)

数字钟电路的实现，可以24小时计时，可调整时间！(Digital clock circuit implementation, a 24-hour timer, adjustable time!)

说明：  利用ISE编写的产生WALSH码的verilog程序，简单易懂，稍稍修改就可以产生出自己想的8 16 32 64位的WALSH码。。(Prepared using ISE verilog code generated WALSH procedures, easy to understand, a little modification can generate their own like the 8,16，32，64-bit code WALSH. .)

VHDL_COUNTING 000_255 液晶显示器 (ĐẾM 000 ĐẾN 255 HIỂN THỊ 液晶电视 BẰNG NGÔN NGỮ VHDL)

ad9850函数发生器 MSP430单片机驱动程序 扫频 DDS(AD9850 DDS)

利用vhdl编写的双端口Ram程序，不带数据纠错处理-VHDL prepared to use dual-port Ram procedures, do not deal with data error correction

AHB master monitor for verification

the transmitter and receiver modules for serial communication