AND2 VHDL 代码

利用FPGA串口通信向上位机发送数据，使用RS232通信协议，向上位机发送8位数据，其中8八个数据位包括4个信息位，经过7-4汉明编码变为7个信息位，而最低位补0，发送的8位数据为2个16进制数，其2个16进制数通过数码管显示。

数字跑表 该跑表具有启动、复位、暂停、暂停后继续计时等功能 能显示的秒计数时间精确到小数点后第二位，即能显示**.**s 按钮设置防抖-Digital stopwatch in the stopwatch with start, reset, suspend, suspended after the time and other functions can show the seconds counting time accurate to the second place after the decimal point, that can show**.** s Anti-Shake button settings

串行数据开发实用代码， 适合初级学习者使用 很不错(Serial data to develop a practical code for primary learners use very good)

说明：  基于altera fpga的fir IP核实现希尔伯特变换，有matlab仿真(Based on Altera FPGA fir IP core to achieve Hilbert transform, matlab simulation)

用FPGA模拟VGA时序、模拟PS/2总线的键盘接口VHDL源代码，基于Xilinx spartan3-VGA FPGA timing simulation, simulation PS/2 keyboard interface bus VHDL source code, Based on Xilinx spartan3

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美国人写的各种类型的fpag设计指导，非常详细的介绍了从fpga的型号，结构，实现，编程，等各个方面的要点。-Written by Americans of all types of fpag design guide, very detailed introduction from the FPGA models, structure, realize, programming, and other aspects of the main points.

用vhdl语言编写的数字逻辑alu设计，实现包括逻辑运算乘法、加法和移位的运算功能，加入流水线处理，适用于初学硬件语言的同学们

个人参与的某国家工程并行排序MATLAB程序，用于FPGA的RTLAB仿真，使用Simulink工具生成HDL代码。测试可用。(Individuals involved in sort of a national engineering parallel MATLAB programs for the FPGA RTLAB simulation, using the Simulink tool to generate HDL code. Test available.)

Verilog HDL 数字设计与综合，夏宇闻译。本书重点关注如何应用verilog语言进行数字电路和系统的设计和验证，不仅讲解语法，更从基本概念讲起，逐渐过渡到编程语言接口以及逻辑综合等高级主题。(The design and synthesis of Verilog HDL digital, Xia Wen translation. The book focused on how to apply the verilog language for the design and verification of digital circuits and systems, not only explain the grammar, the more I start from the basic concept, and a gradual transition to advanced topics such as programming language interface and logic synthesis.)