AND2 VHDL 代码

xilinx公司提供的关于FPGA硬件设计的额时序约束参考资料-xilinx provided on the FPGA hardware design timing constraints of the amount of reference material

verilog语言编写的jtag（边界扫描模块），初学的时候可以看看(verilog language jtag (boundary scan module), a novice when you can look)

this example exchanges the NRZ code to the MANCHESTER code with moore output

基于VHDL的自动售货机实现,包含完整的源代码,锁脚文件以及下载文件-VHDL-based vending machine realize that contains the complete source code, locking pin, as well as download files documents

通过上翻键和下翻键来设置方波信号正负脉冲宽度，利用一排流水灯来显示按键的次数，通过观察流水灯亮的盏数确定占空比（按一次上翻键亮一盏灯，流水灯全亮时占空比调到了最高或者是最低状态，按一次下翻键灭一盏灯，流水灯全灭时占空比调到了最低或者是最高状态）。(Duty cycle of LED lights and adjustable oscilloscope display code)

protel经典教程，并附有一张电路设计原理图(protel classic tutorials, together with a circuit design schematic)

用VHDL语言实现了DES加密算法，其中包含了测试程序，能够进行仿真。(Using VHDL language implementation of the DES encryption algorithm, which contains the test procedures can be simulated.)

用于实现上位机与下位机之间通过RS232协议来进行通讯。(It is used to realize communication between upper computer and lower computer through RS232 protocol.)

8位并行转穿行发送程序，波特率可自行设置，经检验有实用效果(8-bit parallel transfer walk through the sending program, the baud rate can be set up their own practical effect inspection)

七段LED数码管显示译码器设计，将输入的16位二进制数据分别输出到4个数码管上(Seven-segment LED display decoder design, the input of 16 binary data are output to the four digital tube)