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3
说明: 利用vhdl语言编写的译码器程序,采用两种不同方式(The use of language decoder vhdl program, using two different ways)
- 2009-11-17 13:14:45下载
- 积分:1
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比较适合初学学者,而且比较基础。描述的不全面,先看看吧...
比较适合初学学者,而且比较基础。描述的不全面,先看看吧-it‘s best book for beginner!
- 2022-01-22 16:09:31下载
- 积分:1
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FPGA.Implementations.of.Neural.Networks
FPGA神经网络设计(影印本),全英文,很有用(FPGA neural network design (photocopies), all in English, very useful)
- 2008-05-21 21:14:28下载
- 积分:1
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Modelsim
不错的Quartus II 与modelsim结合仿真简介笔记,较为适合初学者,希望对大家有帮助!()
- 2008-06-06 18:16:53下载
- 积分:1
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uart(可综合)
说明: 【实例简介】用Verilog实现uart串口协议,波特率可选9600、19200、38400、115200。8位数据为,1位校验位,1位停止位。
【实例截图】
【核心代码】核心代码包括TX,RX,Baud,FIFO([example introduction] UART serial port protocol is implemented with Verilog, and the baud rate can be 9600, 19200, 38400, 115200. 8-bit data, 1 bit check bit, 1 stop bit.
[example screenshot]
[core code] the core code includes TX, Rx, baud and FIFO)
- 2020-12-08 16:00:16下载
- 积分:1
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alu
verilog code for 8 bit alu
- 2015-06-30 18:49:10下载
- 积分:1
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100例VHDL语言解释,北京理工大学毕业…
VHDL语言100例详解,北京理工大学ASIC研究生出版,这里是51~94个examples-VHDL language of 100 cases explain, Beijing Institute of Technology, Graduate ASIC publication, here is the 51 ~ 94 examples
- 2022-04-16 00:12:16下载
- 积分:1
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XAPP134_SDRAM_VHDL
XAPP134 SDRAM VHDL design file
- 2011-01-19 09:57:21下载
- 积分:1
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exp12
说明: 浙江大学计算机组成实验12指令扩展多周期CPU实现(The implementation of 12 instruction extended multi cycle CPU in Computer Composition Experiment of Zhejiang University)
- 2020-10-09 16:17:35下载
- 积分:1
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hex_counter-2014-10-15
hex_counter
old project, please let me know if need any help
- 2014-12-03 02:21:05下载
- 积分:1