I write the digital phase

说明：  介绍了Displayport规格中lind training的背景研究，设计和实现。(As the requirement for bandwidth continues to increase in the video market, retaining the signal integrity becomes increasingly more difficult. For many of todays commonly used video interfaces, there are devices that can be used to assist in this matter. However, the use of such a device is only partially documented in the DisplayPort specification for the receiving image device, which means that the receiving side of the video link is free to choose its own implementation. This report presents, together with background research and design decisions, a suggestion for such an implementation. This implementation would need to be compatible towards a wide range of possible video Source devices and DisplayPort cables.)

本代码来自老师指导，自己编写，可以修改交通灯的时间

该程序使用Verilog语言产生LFM信号(The program uses Verilog language to generate LFM signals.)

异步串行传输的verilog hdl 功能文件以及测试文件(The verilog hdl source and the testbench of asynchronous serial transmission )

adfvff f fdfs f dvdsz dz vdzsvd hdfdgvaz

频率计 测量范围1-100MHz 测量阈值0.1s 计数部分为FPGA/CPLD 语言VHDL 显示部分为51 单片机加八位数码管 语言C(Frequency meter Measuring range 1-100 MHZ Measure threshold is 0.1 s Count part of FPGA/CPLD Language VHDL Display part of 51 MCU with eight digital tube Language C)

本设计是一个伪随机数发生器。此设计；

通信IC设计的第二章Verilog参考学习代码，方便初学者学习入门，供学习参考用The codes of Chapter1 of《Communication IC Design》(The codes of Chapter2 of《Communication IC Design》)

自己用verilog编写的crc16-ccitt码的产生，是并行的。(Crc16-ccitt code written in verilog generate parallel.)

说明：  VHDL资料 很不错的！！！！！！！！！！！(VHDL )