有关视频压缩的IPCore，希望对大家有用

通信系统帧同步信号的设计与实现，巴克码识别器系统完整VHDL程序，本人课程设计，完全能正常运行，程序运行环境为Quartus II 7.2 (32-Bit)，win7系统。编译码模块、分频模块、门限设置模块、仿真电路和程序都有。相互交流，共同学习！！

GMSK调制基带眼图仿真源代码，基于MATLAB(GMSK modulation baseband eye diagram simulation source code, based on MATLAB)

说明：  常系数有限域乘法器，verilog DHL源码(Constant coefficient finite field multiplier, verilog DHL source)

开源软核处理器OpenRisc的SOPC设计

用verilog hdl语言编写的fpga与片外sram 的读写控制(With the verilog hdl language fpga sram chip with read and write control)

VHDL语言编程简单实例若干，适合于初学者(VHDL language programming simple example, suitable for beginners)

通过vga通讯控制显示器显示七彩条文，通过quartus编译的程序，可用-Communication and Control through the vga display colorful provisions quartus compiled through the procedures that can be used

是一个用vhdl语言编写的pwm程序，可以方便地用来和nios连接，实现对nios的功能扩展。-is a VHDL language with the PWM procedures can be used to facilitate connections and nios, nios to achieve a functional extension.

vhdl code fpga for lcd 2*16

多功能波形发生器VHDL程序与仿真 URAT VHDL程序与仿真 ASK调制与解调VHDL程序及仿真 LCD控制VHDL程序与仿真-Multi-function waveform generator and simulation of VHDL procedures URAT VHDL simulation procedures and ASK modulation and demodulation procedures and VHDL simulation program LCD control and simulation of VHDL