有关视频压缩的IPCore，希望对大家有用

VCP201_CODE is a FPGA source code.

实现BCD码的加法，用VHDL实现，是书籍上配套的-BCD ADDER，Using VHDL

ASK,FSK,PSK,DPSK调制解调的详细仿真代码(ASK, FSK, PSK, DPSK modulation and demodulation detailed simulation code)

说明：  使用vivado和Xilinx开发板实现抢答器，开发板为Xilinx Artix-7(Using vivado and Xilinx development board to achieve the responder, the development board is Xilinx artix-7)

dp_xiliux 的 CPLD Verilog设计实验,时钟演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, clock demo. code test.

Meyers wavelet. DWT VHDL.

verilog code for 3 bit sequence detector

doulos公司出的VHDL学习工具，非常易学易懂！~(doulos company out of the VHDL learning tool, very easy to understand! ~)

国外的VHDL应用例子，大家可一好好参考一下！-abroad VHDL Application examples, we can make reference to a properly!

通信中加扰/解扰算法。FPGA源代码，verilogHDL语言实现，包含测试程序。(Perturbation/perturbation algorithm. FPGA source code, verilogHDL language implementation, including test procedures.)