DDR SDRAM控制器verilog代码及中文说明文档(DDR SDRAM Controller Using Virtex-5 FPGA Devices)

用verilog语言编译的pci协议实现，而且有具体的电路图(Compiled with the verilog language pci protocol implementation, but also the specific circuit)

VGA 640x480 driver in verilog

基于研华采集卡的FIFO双缓存区高速数据采集(FIFO DAQ)

FPGA的学习指南，绝对经典，内容比较超值，我已经细心读过了，讲解清晰，快速入门。-FPGA-study guide, an absolute classic, the content of more value, I have carefully read, and to explain clearly, Getting Started.

共两个文件，一个是对网络芯片W5500进行控制的master spi接口，另一个是w5500命令控制逻辑，命令格式按照w5500芯片的要求，分为地址段，控制段和数据段进行统一控制。此外提供w5500芯片初始化及读写控制流程图。(A total of two documents, one is the master SPI interface for network control chip W5500, the other is a w5500 command control logic, command format in accordance with the requirement of w5500 chip, divided into address segment, unified control and data segments. In addition to provide w5500 chip initialization and read and write control flow chart.)

应用布莱克曼窗实现FIR滤波器，并绘制相应波形图案(Application Blackman window FIR filter, and draw the corresponding waveform pattern)

Implement the 7 segment diplay on spartan 3

基于图像处理的中值滤波VHDL源码,能够实现对图像的滤波(Based on the median filter VHDL source image processing, image filtering can be achieved)

七人表决器，当有四人或四人以上的人同意是，表决通过。每个裁判控制一个开关，高电平表同意，在quartusII上用全加器来实现，当表决通过时，实验箱上的LED灯亮