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提供了利用 GPIF 对 FX2LP 与同步 FIFO CY7C4625-15AC 之间的接口进行设计的源代码(Provides for the use of GPIF FX2LP and synchronization FIFO CY7C4625-15AC to design the interface between the source code)

一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了与之配套的DDR控制器程序！-A VHDL design with the use of powerful 32-bit CPU, this document contains a complete set of DDR controller program!

针对串行存储器M25P80应用的verilog程序-M25P80 serial memory for applications Verilog program

串口通讯，与硬件联通调试过，收发程序是分开的。(Serial Communication)

至于FSK调制原理就不多说了，这里做的一个实验是二进制频移键控。发送一组码元，通过响应的键控电路监测是发1还是发0然后选择频率控制正余弦电路波形。-see

说明：  基于FPGA设计的串口发送及接收程序，波特率可调(FPGA - based serial port sending and receiving)

早迟门（early late gate），比特同步算法，该文档详细的说明了早迟门算法的原理以及具体的实现步骤(Early late gate (early late gate), bit synchronization algorithm, the document explains in detail the principles of early-late gate method and the specific implementation steps)

卷积码编码译码程序以及其modelsim仿真波形文件等(Convolutional code encoding and decoding procedures and the Modelsim simulation waveform file)

温湿度传感器sht30驱动，系统时钟为125M可读出温湿度。(sht30 driver,sysclk=125MHZ)

verilog写的频率计程序的计数模块,-Verilog written procedures for counting frequency meter module,