ALU用VHDL项目

高级FPGA设计__结构、实现和优化,中文翻译版(Advanced FPGA Design- Architecture, Implementation, and Optimization)

design cpu 16 bits by verilog HDL.

使用并行结构对32位数据进行前导零检测，使用Verilog编程(Use parallel structure to the 32-bit data, leading zero detection, using Verilog Programming)

俩个比较好的计数器的vhdl代码：一个是n位通用计数器，一个是的用到的语法比较全面。是比较好的学习资料-Both a relatively good counter VHDL code: one is the generic n-bit counter, one is the syntax used in the more comprehensive. Is a better learning materials

本书共由三篇组成。其中第一篇由第1~3章组成，介绍PCI总线的基础知识。第二篇 由第4~13章组成，介绍PCIExpress总线的相关概念。第二篇的内容以第一篇为基础。(This book comprises a total of three components. The first chapter from the first 1-3 chapters, introduces the basics of the PCI bus. Second by the first 4 to 13 chapters, introduces concepts related PCIExpress bus. The contents of the first to second basis.)

基于SystemC的Uart模型-----文档(SystemC the Uart model of----- document)

自适应均衡器

simple code based on verilog shifter , cla ,clg , ALU ,PC, decoder , tb_top

自己编写的只读存储器ROM16*8的试试很好用的-ROM 16*8

基于verilog的LU分解,本文件包括详细的程序代码，运行文件，以及详细的文档(LU decompose based on verilog)