ALU用VHDL项目

一般网站上都有i2c master模块的代码,但很少有slave的代码,这里就是slave的代码,非常有用.-general website have i2c master module of code, but very few slave code, This is the slave code, very useful.

不错的verilog学习语言资料，详细地对verilog语言中的重要语句应用进行分析。(A good the verilog learn language information, verilog language statement application.)

电子密码锁，采用基于fpga的设计，可以设置6位密码-Electronic code locks, FPGA-based design, can be set 6 password

关于寄存器重命名register reallocation,VHDL-Register on rename register reallocation, VHDL

VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.(SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the )

利用GPIO口模拟I2C通信，驱动富士通MB85RC系列铁电存储器 ** 支持的型号：MB85RC64/64V,MB85RC128/128V,不支持MB85RC16/16V(The master inputs the device address word (8 bits) following the start condition, and then the slave outputs)

uvm验证方法学入门。step by step，适合IC验证人员入门(uvm verification methodology started. step by step, for IC verification personnel entry)

PROGRAMM有助于使40厘米见方与FPGA机器人改变board.The运动遵循顺时针旋转。此外，惯性中心的旋转过程中保持不动。

这是本人设计的一个关于VME总线接口的FGPA程序，FPGA一边连接ARM LPC2294，一边连接VME总线，FPGA采用的XILINX公司的SPARTANII系列，程序包包含完整的工程文件-This is my design of a VME bus interface on the FGPA procedures, FPGA side of the connection ARM LPC2294, while connecting VME bus, FPGA using the XILINX Inc. SPARTANII series, the package contains a complete project file

VHDL的寄存器读写参考，可自己根据要求重新修改，本示范只做参考用-Register read and write VHDL reference to their request to amend in accordance with, the reference model only