7。对于输入密码锁的关键，假设七个林后重置…

512×8bid的FIFO 含工程文件，基于QUARTUs-512 × 8bid the FIFO with the project document, based on the QUARTUsII

艾米电子的verilog HDL描述的DS18B20的程序(Amy verilog HDL description of the procedures DS18B20)

说明：  简单的单周期CPU设计，实现的指令有：算术运算指令、逻辑运算指令、移位指令、比较指令、存储器读/写指令、分支指令、跳转指令、停机指令。(Simple single-cycle CPU design,The instructions implemented are as follows:Arithmetic operation instruction, logical operation instruction, shift instruction, comparison instruction, memory read/write instruction, branch instruction, jump instruction, stop instruction.)

三相PWM整流，实现功率双向流动,可保持直流侧电压稳定(three-phase PWM rectifier, power can bidirectional flow ，can maintain the stable DC voltage)

Rotary Encoder Reading the Rotary Encoder and indicating the selection through a LED placed on the front panel. Events counter for the Rotary Encoder and displaying the events on the front panel Project: events counter for the rotary encoder and displaying the events on the SSD Pmod (Seven-Segments Display Programable module).

adder_array的设计。加法器阵列设计，顶层模块，四步流水，21位(adder_array the design. The adder array design, top-level module, four-step pipeline, 21)

有用的VHDL源代码-useful VHDL source code

基于vhdl开发的频率发生器-Based on the development of frequency generator vhdl

说明：  This is code of UVM CALLBACK function.

Wiggler Clone .JTAG Schematic and PCB in Altium Designer Format