这是用VHDL实现的8位加法器，对新手有点帮助。

quartus ii 环境下，一个完整的利用TEXTIO仿真的源代码，包括读数据文件和输出数据到文件。(Under quartus ii environment, a complete simulation using TEXTIO source code, including reading data files and output data to a file.)

Multiplication in Verilog code

AD9826中文说明书 ，对于学习AD9826元件有很大的帮助。(AD9826 Discription in Chinese)

SDIO Verilog Sourcw code

用VHDL实现十六位移位乘法器 才有移位相加法来实现-Use VHDL to achieve 16-bit shift multiplier shift only the sum of law to achieve

用CPLD驱动扬声器实现音乐的播放，程序是用VERILOG写的，-CPLD driver speakers with music player, the program is written in VERILOG,

利用matlab设计了一个切比雪夫滤波器，并且对滤波器性能进行了仿真分析。(Using the matlab design a chebyshev filter, and has carried on the simulation analysis on filter performance. )

JOP内核字节码获取，很难找的东东，呕血之作-JOP core byte code access, it is difficult to find the price. Zhi for hematemesis

VERILOG五POSPHY LEVEL3电路描述，可综合,已经过检验.-Five POSPHY LEVEL3 Verilog circuit description can be integrated, has been tested.

一些常见的小模块，自己写的，可能不是特别好，仅供参考，主要是分频器、计数器和数码管的显示