这是用VHDL实现的8位加法器，对新手有点帮助。

8051IP 核源代码（VHDL）.RAR-8051IP nuclear source code (VHDL). RAR

说明：  HDB3编码Quartus2 10.0的工程，modelsim仿真，有实物图、仿真图以及源程序，适合做通信原理课程设计的同学参考使用(HDB3 encoding Quartus2 10.0 project, modelsim simulation, there are physical map, simulation diagrams and source code, suitable for students of communication theory courses designed for reference use)

说明：  FPGA接收串口UART发来的指令设定温度报警值，实时采集DS18B20温度传感器并显示，带报警功能(FPGA receives the instruction from UART, sets the temperature alarm value, collects and displays DS18B20 temperature sensor in real time, with alarm function)

QUARTUSII 9.0 下的三级流水线中值滤波工程，vhdl源程序等。可用于fpga做图像预处理。(the three stage pipeline median filter project under QUARTUSII 9 , VHDL source program. which can be used by FPGA to do image preprocessing. )

此代码实现4人表决功能，4人中有三人同意即为通过。(Four voting)

agilex fpga description

说明：  adfvff f fdfs f dvdsz dz vdzsvd hdfdgvaz

fft变换三个中的一个（站长：三个代码算一个）-one of the three fft transfermation code

调制信号后4倍内插的verilog代码，用于基带成型滤波器输入数据(4 times after modulation signal interpolation verilog code, used to baseband shaping filter input data)