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Lpfilter_20190503
说明: 环路滤波器是通信信号调制解调中最重要的一个部分,环路滤波器设计的好坏将直接影响到接收机的性能指标,二阶锁频辅助三阶锁相环路滤波器可以稳定跟踪具有加加速度的信号源,是现代通信中非常实用的技术,本文中详细编写了单载波信号产生模块、信道噪声模块、数字正交下变频模块、鉴频鉴相模块、环路滤波器模块,并包含了完整的testbench模块,对于初学者非常有用。(Loop filter is the most important part of communication signal modulation and demodulation. The design of loop filter will directly affect the performance index of receiver. The second-order frequency locking assisted third-order phase-locked loop filter can stably track the signal source with acceleration speed, which is a very practical technology in modern communication. In this paper, the single carrier signal generation module and channel noise are written in detail Sound module, digital orthogonal down conversion module, frequency and phase detection module, loop filter module, and contains a complete testbench module, which is very useful for beginners.)
- 2020-11-11 01:27:25下载
- 积分:1
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clo
实现时分秒的计数和校正实现时分秒的计数和校正(Realized and correction of minutes and seconds count)
- 2009-12-21 22:52:39下载
- 积分:1
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RISC
32 bit RISC Processor with 3 stage pipeline
- 2010-03-03 00:09:16下载
- 积分:1
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bist coding
内置自修复分析仪
- 2022-02-12 23:55:43下载
- 积分:1
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MAX531串行DA芯片的VHDL驱动,我应经在实际工程中试验过!
MAX531串行DA芯片的VHDL驱动,我应经在实际工程中试验过!-MAX531 serial DA chip VHDL driver, I shall be in the actual project tested!
- 2022-02-05 14:43:19下载
- 积分:1
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SVPWM_FPGA_ContainSourceCode
广东工业大学硕士论文《SVPWM算法优化及其FPGA/CPLD实现》,在详细分析经典SVPWM算法基础上,提出一种优化算法,并在FPGA上实现。论文附录包含VHDL源码。(Guangdong University Thesis " SVPWM algorithm to optimize its FPGA/CPLD realization" in the detailed analysis of the classical SVPWM algorithm is proposed based on an optimization algorithm, and implemented on FPGA. Paper appendix contains VHDL source code.)
- 2013-12-30 16:00:11下载
- 积分:1
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verilog program for iic bus design. the pakege includes iic protocl master progr...
Verilog数字系统设计教程【夏宇闻】原书第十章:IIC总线接口模块设计代码包-verilog program for iic bus design. the pakege includes iic protocl master program and behavel slavle program, even includes testbench and data bat files.
- 2022-01-31 13:13:45下载
- 积分:1
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Visual Basic 编写的,为程序增加扫描功能
Visual Basic 编写的,为程序增加扫描功能-Written in Visual Basic, in order to increase the scanning process
- 2023-05-11 04:15:02下载
- 积分:1
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用于FPGA的反量化算法的HDL编码,包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。...
用于FPGA的反量化算法的HDL编码,包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-FPGA used to quantify anti-HDL coding algorithms, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
- 2022-04-08 04:33:51下载
- 积分:1
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以太网控制器Verilog源码(含有MAC,MII接口)
以太网控制器Verilog源码(含有MAC,MII接口)(Ethernet controller Verilog source code (including MAC, MII interface))
- 2017-08-18 10:32:27下载
- 积分:1