实现一个简单的电子钟，时间（小时，分，秒）可以设置…

FPGA to design in ECU, very help for engineer

de2 vga控制器，也可用于其他板子开发-de2 vga controller board can also be used for other development

A design on a DE270 FPGA with the use of CCD: a camera DC2 and a TRDB LTM after reading from the SRAM.

这是基于MIMO-OFDM的同步算法研究的源程序。本程序采用的极大似然估计的方法。(This is based on MIMO-OFDM synchronization algorithm source code. The program uses the method of maximum likelihood estimates. )

说明：  ? 熟悉IIC协议总线协议，采用IIC总线对图像采集传感器寄存器进行配置，并转换为RGB565格式。 ? 利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。 ? 利用 SDRAM 接口模块的设计，实现了刷新、读写等操作；为提高SDRAM 的读写带宽，均采用突发连续读写数据方式；并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。 ? 利用双线性插值方法实现对图像640×480到1024×768的放大操作。 ? 完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format. Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface. With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA. The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768. Complete the VGA display interface design.)

CH4CH2CH1VHDL 数字电路参考书所有程序7-CH4CH2CH1VHDL digital circuit reference all proceedings 7

adc0809用FPGA控制的采样非常好用的实例 自己看书后终结的-ADC0809

全数字锁相环的verilog源代码-全数字锁相环的verilog源代码

基于cycloneIIFPGA芯片Ep2c5t144c8的解调程序，用VHDL语言生成-CycloneIIFPGA chip-based demodulation Ep2c5t144c8 procedures, using VHDL language generation

使用FPGA完成AGC 自动增益的代码，适合初学者(FPGA to complete the use of AGC automatic gain code, suitable for beginners)