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vhdl_quick-learn
vhdl learnig material............
- 2015-08-07 19:09:24下载
- 积分:1
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asynchronous-clock-boundary
一个关于跨越异步时钟边界传输数据的解决方案(The solution of transfering data across asynchronous clock boundary.)
- 2011-12-21 14:30:54下载
- 积分:1
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这是关于赢vhdl语言变得信号采集卡,很有实用性,大家可以来看看的。...
这是关于赢vhdl语言变得信号采集卡,很有实用性,大家可以来看看的。-This is about winning VHDL language has become signal acquisition card, is very practical, we can take a look at the.
- 2022-08-10 10:21:25下载
- 积分:1
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iq_balance
调整iq幅度不平衡的模块,可以解决载漏和边带问题。(Iq amplitude imbalance adjustment module can be resolved carrier and sideband leakage problems.)
- 2021-04-23 17:48:47下载
- 积分:1
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xapp1251
1. REVISION HISTORY
2. OVERVIEW
3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS
4. DESIGN FILE HIERARCHY
5. INSTALLATION AND OPERATING INSTRUCTIONS
6. SUPPORT
- 2020-11-07 09:49:49下载
- 积分:1
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dspbuilder_manul
这份文献主要介绍了dsp builder 8.0的功能及使用手册,介绍了如何和matlab一起使用的步骤。(This literature focuses on the dsp builder 8.0 features and user manual describes how to matlab and used in conjunction with steps.)
- 2009-10-17 21:00:41下载
- 积分:1
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velocity_Verilog
速度表(velocity)要求:1.显示汽车Km/h数;2.车轮每转一圈,有一传感脉冲;每个脉冲代表1m的距离;3.采样周期设为10s;
4.要求显示到小数点后边两位;5.用数码管显示;6. 最高时速小于300Km/h。(约为83.3m/s)
(use verilog to realize velocity)
- 2020-07-13 15:08:51下载
- 积分:1
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VHDL achieve a frequency measurement of dollars, development environment for any...
一个vhdl实现的测频计,开发环境为任何支持vhdl语言的厂商提供的开发环境
-VHDL achieve a frequency measurement of dollars, development environment for any VHDL language support for manufacturers of the development environment
- 2022-01-28 17:39:53下载
- 积分:1
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State machine used to achieve code lock
用状态机实现密码锁State machine used to achieve code lock-State machine used to achieve code lock
- 2022-10-12 19:25:03下载
- 积分:1
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基于FPGA五子棋显示verilog源代码
基于FPGA的verilog语言描述五子棋游戏中的棋框显示,应用VGA显示原理,用不同的颜色显示边框。以及根据棋子输入的要求,显示相应的棋子,不同的颜色显示不同的棋框和棋子
- 2022-12-19 10:35:03下载
- 积分:1