Verilog很不错的进阶书!看完后对数字模拟集成电路设计有个深入的认识!...

蓝牙HCI―UART与并口的FPGA控制接口设计-Bluetooth HCI-UART and parallel port control interface of the FPGA design

能够完美产生数字地面电视（DTMB）的信源的程序。帧头模式为模式一。信道可选择，信号加入频偏，延时，后经滤波器后输出。(Able to produce perfect digital terrestrial television (DTMB) of the source program. Mode is the mode a header. Channels to choose from, the signal adding offset, delay, after the filter output.)

ise13.2环境下VHDL编写的半加器器+仿真波形(ise13.2 environment half adder in VHDL simulation waveform control+)

这是本人写的可显示128*64LCD全屏汉字的程序,直接下到片子里即可出现象(需自己定制ROM).想显示第二屏的话只需加一个状态即可.-I write this is the display of 128* Embedded full screen characters procedures, directly to the unit under the blankets will be out phenomenon (it-yourself customized ROM). to the second screen shows only the state can be a plus .

SEG7数码管显示示例程序，适用于ALTERA的CPLD(SEG7 digital display sample program of ALTERA CPLD)

I2C接口标准建模源码,I2C interface standard modeling source-I2C interface standard modeling source

基于fpga和xinlinx ise的音乐播放器vhdl程序，希望对你有所帮助！-and xinlinx ideally music player VHDL process, and I hope to help you!

一个在FPGA芯片上实现UART功能的vhdl源代码，提供了UART的集成-an FPGA chip to achieve UART function vhdl source code, providing integrated UART

系数为4的扰码生成器，并每四位扰码产生一个触发串并转换的触发信号，可用于4b/5b编码的触发信号。verilog程序，带test程序-coefficient of the four scrambler generator, and every four scrambler have triggered a string conversion and the trigger signal can be used to trigger 4b/5b coding signal. Verilog procedures, with test procedures

AM modulated learning ladder