Vhdl practical tutorials to help beginners to grasp quickly the preparation of V...

verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，11-12章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code 11-10-12 Cap

FIFO的VERILOG代码编写 可综合的Verilog FIFO存储器(The VERILOG code FIFO write comprehensive Verilog FIFO memory)

sdram 代码在最后要强调的是，本专题以技术为主，由于篇幅的原因，不可能从太浅的方面入手，所以仍需要有一定的技术基础作保证，而对内存感兴趣的读者则绝不容错过，这也许是您最好的纠正错误认识的机会！

verilog实现DLX指令集5段流水线(5 stage DLX pipeline implemented in verilog)

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity song is    port(clk_4MHz,clk_4Hz:in std_logic;      ----预置计数器和乐谱产生器的时钟         digit:buffer std_logic_vector(6 downto 0);  ----高、中、低音数码管指示         zero:out std_logic_vector(4 downto 0);     ----用于数码管高位置低  

verilogHDL语言编写，简单的FPGA脉冲程序，初学者必备。(verilogHDL language, a simple FPGA pulse program, beginners must.)

说明：  LTE is an abbreviation for Long Term Evolution.

Huffman encoder decoder verilog

PS2键盘硬件模块控制器，主要实现硬件PS2键盘的控制，适合初学verilog学者实验。(PS2 keyboard controller hardware module, the main hardware PS2 keyboard control, suitable for beginners verilog scholar experiments.)