HDL example source code 1/5 tff_a

quartus环境下开发的三人表决器（三种不同的描述方式）maxplusII兼容

FIR filter up to 128x

csapp 第二版 体系结构实验 答案 第三个部分能跑58分(the second edition csapp architecture experiment the third part of the answer can run 58 minutes)

JOP字节码获取的源码，很重要，具体FPGA中实现-JOP byte code access to the source code is important to achieve specific FPGA

LDPC码不同码长对比。码率选择1/2.码长分别为256，512，1024.(LDPC codes of different code length contrast. Bitrate select 1/2 yards long were 256,512,1024.)

altera max10 USB demo，使用了phy，把开发板配置成U盘模式(altera max10 USB demo，using PHY device，design a U pan)

基于Verilog HDL的完整数字跑表工程，在试验机台上运行验证通过了的。 用8位7段数码管分别显示微妙，秒，分。 有开始，暂停，复位功能。 学习VerilogHDL的经典例子，添加了显示功能。-Complete Verilog HDL-based digital stopwatch works in the test machine is running verify pass the platform. With 8-bit 7-segment digital tube showed the delicate, seconds, minutes. Has started, pause, reset. Learning VerilogHDL classic example of adding a display.

Wimax矩阵的LDPC编码器，已通过modelsim仿真测试，并前在altera的FPGA板上通过测试,码率5/6，可进入代码内部修改参数，支持2/3,3/4其他2个码率，数据吞吐量为700M(Wimax based LDPC encoder, modelsim simulation passed, also passed on altera FPGA board, code rate 5/6, also support 2/3,3/4, throughout 700m)

坦克游戏用VHDL语言编写。Altera的随身携带套件DE1。PS2键盘接口和VGA

this program is a simulation for Aloha