HDL example source code 1/5 tff_a

说明：  (Springer Series in Advanced Microelectronics 51) Ayan Palchaudhuri, Rajat Subhra Chakraborty (auth.)-High Performance Integer Arithmetic Circuit Design on FPGA_ Architecture, Implementation and Desig

用Verilog语言实现了UART串行通信协议(Verilog language used to achieve a UART serial communication protocol)

encoding and decoding of audio signal

说明：  频率合成器实例模块设计。频率分辨率为32位DDS的VHDL程序(Frequency synthesizer module design example. 32-bit DDS frequency resolution of the VHDL program)

对aurora模块时钟处理模块，实现时钟的分频等处理(Aurora module clock processing module,Clock frequency division and other processing)

xilinx edk 9.2 破解器/注册机(xilinx edk 9.2 crack)

8051参考设计，与其他8051的免费IP相比，文档相对较全，Oregano System 提供-8051 reference design, and other free IP in 8051 compared to relatively entire document, Oregano System for

在开发板EGO1上实现赛车游戏,语言为verilog，内含bits文件(racing game in verilog)

基于FPGA的图像压缩算法程序，自己写的，可以参考一下(FPGA-based image compression algorithm, write your own, you can refer to)

本代码为简单AXI接口控制模块，具备数据的读写等传输功能，对总线传输学习者来说是很好的学习资料，可在此代码基础上进行更复杂功能接口的模块的开发。