FIR滤波器高达128倍

Turbo码编解码的FPGA实现，verilog语言编写(Implementation ofTurbo code on FPGA , using Verilog language)

The code is used to interface PC monitor with Spartan 3E for the display. if you run the program on spartan 3 you would be able to see different test pattern on the monitor screen

本代码绝对真实可靠，原用于长沙理工大学EDA课程设计之出租车计费器。本代码在要求的基础上添加显示时速和报警功能。希望此代码对有此需求的同学有所帮助！

说明：  基于fpga的verilog实现ad及uart，并进行仿真验证(Verilog based on FPGA implements AD and uart, and carries out simulation verification)

ASIC design and synthesis

梁祝音乐verilog code --适用于QUATUS II 开发环境下，适合于verilog入门学员(the verilog code of liangzhu )

FPGA经验总结：时序是设计出来的 我们在做详细设计的时候，对于一些信号的时序肯定会做一些调整的，但是这种时序的调整最多只能波及到本一级模块，而不能影响到整个设计。(FPGA Experience: Timing is designed to do the detailed design of our time, for some signal timing will certainly make some adjustments, but adjust this timing can only spread to up to this level of the module, but not affect the whole design.)

MAX481、MAX483、MAX485、MAX487-MAX491以及 MAX1487是用于RS-485与RS-422通信的低功耗收发器， 每个器件中都具有一个驱动器和一个接收器(The MAX481, MAX483, MAX485 The MAX487-MAX491, and MAX1487 low-power transceivers for RS-485 and RS-422 communication, each device has a drive and a receiver)

异步FIFO的设计 包括testbench 已调试成功-Asynchronous FIFO design includes testbench debug success has been

fpga正弦波发生函数，可用于自动生成rom文件(fpga sine wave generating function)