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该代码在信令模块MK50H27 CPLD第七满足(Xilinx 95144)罗…
该代码为配合7号信令模块MK50H27的cpld(xilinx 95144)的逻辑代码,其中包括了VHDL及原理图.-the code to meet on the 7th of signaling modules MK50H27 cpld (Xilinx 95144 ) logic code, which included a schematic and VHDL.
- 2023-05-01 09:05:04下载
- 积分:1
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qts_qii55002
ALTERA on chip fifo. this document is from altera. good resouce
- 2010-09-26 22:12:17下载
- 积分:1
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shuzijishiqi
基于VHDL的数字计时器,手动可控正计时和倒计时(含复位键和使能键)(VHDL-based digital timer and countdown timer being controlled manually (with the reset button and enable key))
- 2016-12-05 19:57:07下载
- 积分:1
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93 std
-- Booth Multiplier
-- This file contains all the entity-architectures for a complete
-- k-bit x k-bit Booth multiplier.
-- the design makes use of the new shift operators available in the VHDL-93 std
-- this design passes the Synplify synthesis check
-- download from: www.fpga.com.cn & www.pld.com.cn--- Booth Multiplier-- This file contains a ll the entity-architectures for a complete-- k- bit x k-bit Booth multiplier.-- the design mak es use of the new shift operators available in th e VHDL-93 std-- this design passes the Synplify synthesis check-- download from : www.fpga.com.cn
- 2022-02-25 16:35:00下载
- 积分:1
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fpga_debounce_filter
fpga debounce filter code in vhdl
- 2009-10-02 18:48:22下载
- 积分:1
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FPGA
fpga 设计全攻略,很好的fpga入门提高资料(the fpga design Raiders, good fpga the Getting Started improve data)
- 2012-12-09 19:03:23下载
- 积分:1
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verilog编写的计算百分比模块
verilog编写的计算百分比模块-Verilog prepared by calculating the percentage module
- 2022-01-31 18:38:18下载
- 积分:1
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官方的RS232例程详细Altera非常实用
altera 官方rs232例程 很详细很实用-official rs232 routines in great detail altera very practical
- 2023-04-15 09:15:03下载
- 积分:1
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(Oxford)-Computer-Arithmetic--Algorithms-a-Hardwa
Computer Arithmetic (press 2000)
- 2012-01-27 09:45:29下载
- 积分:1
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Altium Partner SN-1000010 r10
说明: Browser modularization processing, browser modularization combing, browser modularization expansion
- 2020-06-24 04:20:01下载
- 积分:1