a program which divides the clock by 3

FPGA to design in ECU, very help for engineer

UC1701串行编程例子，是一个很好的控制ＬＣＤ模块的Ｃ语言串行编程(UC1701 serial program)

实用的程序代码，希望对大家有用，已经调试通过-Practical program code, in the hope that useful to everybody, has debugging through

基于CPLD器件EPM570，用VHDL语言编写的并串转换器代码，用于实现并行代码到串行代码的转换

一个三分频verilog模块，可以用来学习基本结构。(A three points frequency verilog module can be used to study the basic structure.)

快速实现HDB3码与普通码二进制码的转换，方便学习与了解HDB3码的转换(Quickly achieve HDB3 code and common code binary code conversion, facilitate learning and understanding HDB3 code conversion)

cpld/fpga常用加法器设计的verilog程序-cpld/fpga common adder Verilog design procedures

this program does something im not sure what but all i want is to get into the damn site thank you

Advanced FPGA Design Architecture, Implementation, and Optimization

基于VHDl的2FSK调制！用的是altera的quartus11软件(Based on VHDl the 2FSK modulation)