LMP

八位并行数据转换为串行数据依时钟信号串行输出(Eight bit parallel data to serial data)

1 由matlab计算FIR数字滤波器的滤波系数； 2 用VHDL语言设计逻辑电路，再通过QUARTUS II 软件，将各个模块的电路封装成期间，在顶层设计中通过连线，完成整个系统。 (matlab VHDL QUARTUS )

说明：  本例的源描述超过了演示版限制的300行, 如果您需要对其进行编译与模拟,请与北京理工大学 ASIC研究所联系,获取Talent系统的完全版本. 联系方法: 电话:010-68912434 (The source described in this case than the demo version of the 300 line limit, if you need to be compiled with the simulation, please contact ASIC Institute of Beijing Institute of Technology to obtain the complete version of Talent system. Contact: Tel :010-68912434)

Synopsys 8051 IP core documentation.

基于FPGA实现的神经网络算法ANN。针对手势识别，不错的参考文章。(Hand Postures Recognition System Using Artificial Neural Networks Implemented in FPGA)

用VHDL语言编程完成数码管0-255数字的显示-VHDL language programming with the 0-255 number to complete the display of the digital control

说明：  本书从电子技术和通信系统的角度讲解gps接收机的设计开发原理，其内容集中在用户终端，即接收机的设计原理和软件实现上。全书分为两大部分，第一部分为理论篇，第二部分为实现篇。理论篇首先对导航的基本目的进行了阐述，并由一个浅显的二维导航系统对导航信号的特点进行了推导，随后阐述了gps信号格式，同时对于直接影响接收机性能的射频前端部分做了理论分析；实现篇主要对本书实现的软件gps接收机的系统实现和源代码进行了讲解，同时作为总结，将信号处理的结果和有意义的中间变量以图示的方式给出，可以使读者有一个感性的认识，同时提升学习兴趣。. 本书适合从事卫星导航接收机研发的技术人员和卫星通信接收机研究的研究人员，尤其是从事北斗系统研发的专业人员、cdma通信系统研发人员，以及通信电子类专业的高年级本科生和研究生阅读，既可作为教学培训的教材，也可作为相关专业工程技术人员的参考资料。(This book explains the design and development principle of the GPS receiver from the perspective of electronic technology and communication system. Its content focuses on the design principle and software implementation of the user terminal, that is, the receiver. The whole book is divided into two parts. The first part is the theoretical part and the second part is the realization part. Firstly, the basic purpose of navigation is expounded, and the characteristics of navigation signal are deduced by a simple two-dimensional navigation system. Then, the format of GPS signal is expounded. At the same time, the front-end part of radio frequency which directly affects the performance of the receiver is theoretically analyzed.)

说明：  该模块实现了FPGA的uart串口收发功能(The module realizes UART serial port transceiver function of FPGA)

利用VHDL语言编写的4*4键盘扫描程序，经过测试，可以放心使用。(Using VHDL language 4* 4 keyboard scanning procedures, tested, safe to use.)

A VANET research program