LMP

基于CPLD 的光电脉冲码盘 信号四倍频电路设计-CPLD-based electro-optical pulse encoder signals four multiplier circuit design

自动售货机，投币自动售货 MaxplusII下运行-Vending machines, coin-operated automatic vending MaxplusII run

说明：  basic verilog code on siso, piso, sipo

AGC(自动增益放大) Verilog代码 设计可以参考 第二部分(AGC (automatic gain control) can refer to the Verilog code design )

红外接收处理，根据外部波形记录波形的高低电平时间，从而得到波形数据。(Infrared receiver processing, according to the external waveform waveform record high and low times, resulting waveform data.)

使用VerilogHDL语言加上IP核产生PWM调制波，占空比和频率可调。(The PWM modulation wave, duty cycle and frequency can be adjusted by using VerilogHDL language and IP kernel..)

VHDL_count 从 0000 到 9999 7 段 LED 显示器 （đếm 慈 0000 đến 9999 hiển 施耐 4 领导 7 đoạn）

这是一个fft的IP核，安装要求为quartus6.0以上。解压安装后可在quartus里例化使用，元件主要为cyclone和stratix,最大支持1024点的转换。

基于FPGA的Mcbsp通信源码，经过项目实测检验(Mcbsp communication source code based on FPGA,Through the test of the project.)

parity encoder test bench