LMP

说明：  适应多个模式的rs编码，Verilog，选择对应的多项式(RS coding adapted to multiple modes.)

OFDM系统新型CC编解码的verilogHDL设计，与RS编码级联，经测试误码率性能提高(OFDM system verilogHDL new CC codec design, coding and RS cascade, tested BER performance improvement)

FPGA编程，经过团体奋战完成，全是底层的IIc和sci通信，完整版。(FPGA programming, after groups fight to the finish, all underlying SCI and IIc communication, full version)

　　本文对数字基带信号脉冲成型滤波的应用、原理及实现进行了研究。首先介绍了数字成型滤波的应用意义并分析了模拟和数字两种硬件实现方法，接着介绍了成形滤波器设计所需要MATLAB软件，以及利用ISE system generator在FPGA上进行滤波器实现的优势。文中给出了成形滤波函数的数学模型，讨论了几种常用成形滤波函数的传输特性以及对传输系统信号误码率的影响。然后介绍了本次设计中使用到的数字成形滤波器设计的几种FIR滤波器结构。把各种设计方案进行仿真，比较仿真结果，最后根据实际应用的情况并结合设计仿真中出现的问题进行分析，得出各种设计结构的优缺点以及适合应用的场合。(In this paper, the application of the principles and implementation of digital baseband signal pulse shaping filter is studied. First introduced the significance of digital shaping filter application and analysis of both analog and digital hardware implementation, then introduces the shaping filter design requires MATLAB software, and the use of ISE system generator on the FPGA to achieve the advantages of the filter. This paper presents a mathematical model of shaping filter function, the transmission characteristics discussed several common shaping filter functions and the impact on the error rate of the signal transmission system. Then introduced the use of this design to several digital shaping filter design FIR filter structure. The various design simulation, compare the simulation results, and finally according to the actual application and combine design simulation to analyze problems, come and where appropriate to the application advantages and disadvantages of various design s)

在FPGA开发板上用VHDL语言实现了贪吃蛇游戏，开发软件为quartus 2.这是详细的实验报告，包括源码(Snake game with VHDL FPGA development board, software development quartus 2 This is a detailed experimental report, including the source)

FPGA Verilog HDL模拟IIC通讯接口-FPGA Verilog HDL IIC Interface

mico8  vhdl  project lattice出的小资源mcu 256luts  值得学习

VHDL，verilog串并转换源程序 Xilinx公司参考资料-VHDL, verilog Series and conversion company Xilinx reference source

说明：  在zedboard上运行的神经网络架构，方便移植。(Run lenet-5 on zedboard)

说明：  用VHDL实现密码锁功能，用状态机实现，分管理员和用户两种功能，可分别修改密码，重置密码等。(codelock，VHDL，state)