soft for changing Verilog code to c++ code ,c code

利用VHDL实现CPLD（EPM240T100C5）的VGA屏幕输出-Using VHDL realize CPLD (EPM240T100C5) output of the VGA screen

数字钟：实验中用到的小程序，用于万年历中的模块(Digital clock: a small program used in the experiment, the modules for calendar)

ALTERA NIOS处理器，VHDL语言在QUARTUS编译通过，然后有C语言在NIOS SHELL下驱动，实验音频解码-Altera NIOS processor, the QUARTUS VHDL compiler, then the C language under NIOS SHELL-driven, experimental audio decoder

用verilog实现了一个数字秒表的设计-verilog achieved using a digital stopwatch Design

开关电源变换器（Switching Power Supply）为当前电子产品中应用非常广泛的功率器件，在日常生活中无处不在

基于VHDL语言的七段显示管程序， 实现9个数字循环 并且能控制播放速度(SEVEN SEGMENT DISPLAY)

basic cpu design in verilog

this files describes how to build i2c block modules in verilog hdl and programming them on an fpga device

fpga的一些经验之谈，对初学者比较有用，都是些容易出错误的地方(FPGA some experiences, more useful for beginners, are more vulnerable to the wrong place)

说明：  实现了QPSK的调制，使用了ise自带的dds的IP核(QPSK is modulated and the IP core of DDS is used in ise.)