VHDL实现led灯的动态扫描，主要对CLK进行分频

说明：  ADD MOV MOVi SUB四指令cpu设计，qutartus，(Design of four-instruction CPU)

说明：  Xilinx Licenses 2018

状态机的性能考察.rar 状态机的性能考察.rar-Study the performance of state machine. Rar inspect the performance of state machine. Rar

实现verilog读写txt文件，从sut.txt从读取数据，进行操作后，写入out.txt(Realize verilog read and write txt file)

实现米粒状态机 用verilog语言实现状态机的过程(Implement a state machine with a grain of rice verilog state machine language course)

This is verilog source code for DES(Data Encryption standard) which is used in network security.

TDM，就是时分复用。本程序完成4通道，没通道最多32路64K信号的交换，就是说可以完成32x4个电话信号交换(TDM, is time-division multiplexing. The process is complete 4-channel, no channel up to 64K 32 to exchange signals, that can be done 32x4 telephone signal exchange)

几大代工厂的flash verilog源代码(flash verilog code)

用VHDL语言设计篮球24秒可控计时器功能说明：1.具有24秒计时、显示功能；              2.设置外部按键，完成清零、暂停、恢复控制；              3.24秒倒计时，时间间隔为1s；               4.时间到后发出报警信号，并在3s后解除。

VHDL语言编写的计数器程序，实现1到9999计数，并动态扫描显示，带清零和暂停功能，课上作业自编程序-VHDL language of the counter program to achieve 1-9999 counts, and the dynamic scan showed, with Clear and suspension of functions, classes, on a self-compiled programs