基于FPGA的多功能电子时钟的设计很经典的哦

使用VHDL编写语言，巧妙的利用计数器和循环输出一个坐标系，由于VHDL出现负数比较麻烦，全部由正数代替，输出一个原点在中心，半径128的256×256的坐标。方便坐标变换以及用此坐标做算法。(Use of VHDL language, clever use of counter and loop outputs a coordinate system, because VHDL negative too much trouble, all replaced by a positive number, the output an origin at the center, radius 128 256 256 coordinates. Convenient coordinate transformation and coordinate to do with this algorithm.)

verilog数字系统设计，一本很好的verilog学习的书籍，很适合初学者(verilog digital system design, a good verilog learning books, it is suitable for beginners)

浙江大学体系结构实验课代码 实现5级流水线带有停顿，旁路和控制竞争的处理。(Experimental Architecture, Zhejiang University course code with a pause 5-stage pipeline, bypassing the treatment and control of competition.)

spwm dcac逆变 fpga与单片机一起作用(sdad)

matlab dsp building 工程欢迎下载(matlab dsp building )

verilog 驱动TLC5510代码，TLC5510是高速的AD，可达20MHz(verilog code driven TLC5510, TLC5510 is a high-speed AD, up to 20MHz)

Anticipated Adder for Xilinx

verilog写的39阶通带为20KHz的半带fir滤波器，经测试正确。(verilog halfband FIR)

NAND型闪存接口程序 里面包含了datasheet以及测试程序 (NAND flash memory interface program)

verilog 编写的I2C程序，控制D/A的(I2C program written by Verilog to control D/A)