学习应用FPGA pid实现

4 seg display, button debouncer, and controller for parking meter

序列检测VHDL源代码，ATERA平台编译。详细的报表说明和模拟源代码。

　　本文对数字基带信号脉冲成型滤波的应用、原理及实现进行了研究。首先介绍了数字成型滤波的应用意义并分析了模拟和数字两种硬件实现方法，接着介绍了成形滤波器设计所需要MATLAB软件，以及利用ISE system generator在FPGA上进行滤波器实现的优势。文中给出了成形滤波函数的数学模型，讨论了几种常用成形滤波函数的传输特性以及对传输系统信号误码率的影响。然后介绍了本次设计中使用到的数字成形滤波器设计的几种FIR滤波器结构。把各种设计方案进行仿真，比较仿真结果，最后根据实际应用的情况并结合设计仿真中出现的问题进行分析，得出各种设计结构的优缺点以及适合应用的场合。(In this paper, the application of the principles and implementation of digital baseband signal pulse shaping filter is studied. First introduced the significance of digital shaping filter application and analysis of both analog and digital hardware implementation, then introduces the shaping filter design requires MATLAB software, and the use of ISE system generator on the FPGA to achieve the advantages of the filter. This paper presents a mathematical model of shaping filter function, the transmission characteristics discussed several common shaping filter functions and the impact on the error rate of the signal transmission system. Then introduced the use of this design to several digital shaping filter design FIR filter structure. The various design simulation, compare the simulation results, and finally according to the actual application and combine design simulation to analyze problems, come and where appropriate to the application advantages and disadvantages of various design s)

RS232的UART编程，包括波特率发生器模块，串口接受模块，串口发送模块(RS232 programming the UART, including the baud rate generator module, serial module to receive, send serial module)

说明：  发送两个频段的脉冲 个数和频率均可调 发送两个频段的脉冲 个数和频率均可调(pluse and adjust the width of pluse pluse and adjust the width of pluse )

提供了利用 GPIF 对 FX2LP 与同步 FIFO CY7C4625-15AC 之间的接口进行设计的源代码(Provides for the use of GPIF FX2LP and synchronization FIFO CY7C4625-15AC to design the interface between the source code)

DAC0832 VHDL源程序 一个适合初学都的程序 (DAC0832 VHDL source code of a program suitable for both beginners)

FPGA经验总结：时序是设计出来的 我们在做详细设计的时候，对于一些信号的时序肯定会做一些调整的，但是这种时序的调整最多只能波及到本一级模块，而不能影响到整个设计。(FPGA Experience: Timing is designed to do the detailed design of our time, for some signal timing will certainly make some adjustments, but adjust this timing can only spread to up to this level of the module, but not affect the whole design.)

用Verilog代码实现的乒乓操作，用Verilog代码实现的乒乓操作(Verilog pingpong)

将BT656数据流转换成RGB图像格式的数据(Converting BT656 data stream into RGB image format)